 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| bt brook t ree brooktree corporation ? 9868 scranton road ? san diego, ca 92121-3707 ? 619-452-7580 1-800-2-bt-apps ? fax: 619-452-1249 ? internet: apps@brooktree.com ? l211501 rev. c mediastream controller distinguishing features local bus graphics controller (glueless for): pci 2.0 bus vesa vl 2.0 bus (32 bit) 32 bit vram (1mb to 4mb) samsung ? 256kx8: -8,-7,-6 128kx16:-8,-7,-6 texas instruments ? 256kx16:-8,-7,-6 nec ? , toshiba ? , ibm ? 256kx16:-8,-7,-6 up to 1mb of flash rom supports yamaha 2 and 4 operator mode fm synthesizer family resolutions: 640x480: 4, 8, 16, 24, 32 b/pixel up to 76 hz 800x600: 4, 8, 16, 32 b/pixel up to 76 hz 1024x768: 4, 8, 16, 24 b/pixel up to 75 hz 1280x1024: 4, 8, 16 b/pixel up to 75 hz vga compatibility for modes 0x00 - 0x07 and 0x0d - 0x13 multimedia solution glueless connection btv2811a videostream decoder acceleration of two video planes with hardware double buffering hardware-accelerated video playback stereo audio in/out software encoded ntsc/pal video out to vcr stretch blt and raster scaling legacy audiopro ? compatibility digital interface to consumer digital audio tape, minidisc, etc. standard interfaces pci bus 2.0 compatible vesa vl bus 2.0 aes/ebu s/pdif cp-340 (with full access to channel/user bits) ? 2 c/ access.bus vesa ddc1, ddc2a/b vesa dpms 208 pin power quad package applications microsoft windows ? 3.1, win ?5 ? , and nt ? gui acceleration ibm os/2 ? gui acceleration xwindow system ? acceleration video for windows ? and microsoft windows mpc audio ? high resolution color graphics video-conferencing multimedia applications video playback acceleration btv2115 related products btv2487 pacdac btv2811a videostream decoder btv2300 audiostream interface functional block diagram d ata a ddress c lock i nterrupt pci / vl b us i nterface d ata a ddress c ontrol m emory c ontroller v ideo i nput i nterface vga m edia b uffer a ccess gui a ccel a udio i/o clk17 mm_c lock mm_d ata pacdac s erial c lock c ontrol c locks d ata vrdy c lock g eneration clk25 audclk_out 50 mh z 100 mh z t est i 2 c iic i/o ddc i/o tm s oftware e ncoded v ideo o utput c ontrol advance information this document contains information on a product under development. the parametric information contains target parameters that are subject to change.
copyright 1994, 1995 brooktree corporation. all rights reserved. print date: 08/30/95 brooktree reserves the right to make changes to its products or speci?ations to improve performance, reliability, or manufacturability. information furnished by brooktree corporation is believed to be accurate and reliable. however, no responsibility is assumed by brooktree corporation for its use; nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by its implication or otherwise under any patent or patent rights of brooktree corporation. brooktree is a registered trademark of brooktree corporation. brooktree products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a brooktree product can reasonably be expected to result in personal injury or death. brooktree customers using or selling brooktree products for use in such applications do so at their own risk and agree to fully indemnify brooktree for any damages resulting from such improper use or sale. brooktree and bt are registered trademarks of brooktree corporation. ultralock and bytestream are trademarks of brooktree corporation. all other marks mentioned herein are the property of their respective holders. speci?ations are subject to change without notice. printed in the united states of america model number package ambient temperature range btv2115ksf 208 pqfp 0?c to +70?c BTV2115AHF 208 plastic mqfp 0?c to +50?c ordering information trademarks brooktree and btv are registered trademarks of brooktree corporation. the following are trademarks of brooktree corporation: videodac, ramdac, video cachedac, videocache, pacdac, bytestream, fastick, and mediabuffer. winbench is a registered trademark and winstone is a trademark of ziff-davis publishing company, l.p. in compliance with ziff- davis?licensing agreement: benchmark tests were obtained with winbench 4.0 run on a dell dimension xps p90 minitower pentium 90mhz, 256k sram cache, 16m system memory, and the btv2115ksf pci-bus graphics adapter. dell is a registered trademark and dimension xps p90 is a trademark of dell computer corporation . compaq and deskpro are registered trademarks and eisa is a trademark of compaq computer corporation. intel is a registered trademark and pentium is a trademark of intel corporation. microsoft and ms-dos are registered trademarks and windows, win ?5, windows nt, plug and play, windows mpc audio , and video for windows are trademarks of microsoft corporation. philips is a registered trademark of philips international b.v. access.bus is a trademark of digital equipment corporation. tri-state is a trademark of national semiconductor. micro channel architecture (mca) and os/2 are trademarks of ibm corporation. vesa is a registered trademark of and vl-bus and vbe are trademarks of video electronics standards association. xwindow system is a trademark of massachusetts institute of technology. yamaha opl2/3/4 are trademarks of yamaha corporation. samsung is a trademark of samsung electronics co., ltd nec is a trademark of nec corporation. toshiba is a trademark of toshiba corporation. ibm is a trademark of ibm corporation. all other marks mentioned herein belong to their respective companies. brook t ree iii bt t able of c ontents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii what this document contains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxix notation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxx product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 cpu/host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 vram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 pacdac interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 multimedia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 i 2 c interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 serial audio interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 distinguishing features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 applications and related products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 btv2115 vl-bus pin list summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 btv2115 pci-bus pin list summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 t able of c ontents btv2115 brook t ree iv bt vga implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 vga compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 vga operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 simultaneous operation with other btv2115 modules . . . . . . . . . . . . . . . . 20 vga and pacdac controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 vga extension registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 enable vga crt controller mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 enable vga crt controller structure generation . . . . . . . . . . . . . . . . . . . 25 pacdac pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 mhz pll select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 28 mhz pll select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 attribute index status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 vga crt generation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 vga vertical sync select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 vga read latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 vga dac mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 con?uration for vga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 support for vesa bios extension modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 vbe modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 frame buffer models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 timing structures and high resolution modes . . . . . . . . . . . . . . . . . . . . . . 29 mode setting procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 logical window control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 dac palette format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 register de?itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 vga graphics registers (i/o mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 graphics index port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 register name: grp_index graphics data port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 register name: grp_data set/reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 register name: grp_sr enable set/reset register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 register name: grp_esr color compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 register name: grp_cc data rotate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 register name: grp_rot t able of c ontents btv2115 brook t ree v bt read map select register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 register name: grp_rdpln mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 register name: grp_mode graphics miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 register name: grp_misc color don? care register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 register name: grp_ccx bit mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 register name: grp_bitmask extension registers accessed via vga space (i/o mapped) . . . . . . . . . . . . 44 vga con?uration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 register name: grp_vgacfg chip id registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 register name: grp_cid[1:0] rom page register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 register name: grp_rompage pll25 select registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 register name: grp_25pll[2:0] pll28 select registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 register name: grp_28pll[2:0] gui base registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 register name: grp_gui_base[3:0] dac alias pointer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 register name: grp_pdac[1:0] read latch registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 register name: grp_rdlat[3:0] vga status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 register name: grp_vgastat con?uration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 register name: grp_cfg[7:0] i2c control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 register name: grp_i2c_ctrl i2c slave control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 register name: grp_i2c_sctrlr, grp_i2c_sctrlw i2c slave data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 register name: grp_i2c_sdata i2c master control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 register name: grp_i2c_mctrlr, grp_i2c_mctrlw i2c master data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 register name: grp_i2c_mdata master structure a address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 register name: pdc_msptra[2:0] master structure b address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 register name: pdc_msptrb[2:0] t able of c ontents btv2115 brook t ree vi bt pacdac controller status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 register name: pdc_stat pacdac controller control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 register name: pdc_cntl vga pci con?uration space (i/o mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 read pci prefetchable base address register. . . . . . . . . . . . . . . . . . . . . . 59 register name: grp_pbase read pci rom base address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 register name: grp_rombase read pci enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 register name: grp_pci_en sev registers (i/o mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 softvideo controller write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 register name: grp_sv_ctrlw[3:0] softvideo controller read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 register name: grp_sv_ctrlr[3:0] vga sequencer registers (i/o mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 sequencer index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 register name: seq_index sequencer data port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 register name: seq_data reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 register name: seq_rst clocking mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 register name: seq_clk map mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 register name: seq_wpmask character map select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 register name: seq_cfs memory mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 register name: seq_mmode vga sequencer extension registers (i/o mapped) . . . . . . . . . . . . . . . . . . . . 67 unlock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 register name: seq_unlock vga crt controller (i/o mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 crtc color index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 register name: crt_index_c crtc monochrome index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 register name: crt_index_m crtc color data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 register name: crt_data_c crtc monochrome data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 register name: crt_data_m t able of c ontents btv2115 brook t ree vii bt horizontal total register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 register name: crt_htot horizontal display end register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 register name: crt_hdsp_end start horizontal blank register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 register name: crt_hblank_st end horizontal blank register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 register name: crt_hblank_end start horizontal sync register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 register name: crt_hsync_st end horizontal sync register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 register name: crt_hsync_end vertical total register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 register name: crt_vtot over?w register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 register name: crt_overflow preset row scan register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 register name: crt_pre_rs character height register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 register name: crt_cheight cursor start register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 register name: crt_cur_st cursor end register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 register name: crt_cur_end start address high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 register name: crt_screen_sth start address low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 register name: crt_screen_stl cursor location high register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 register name: crt_cur_loch cursor location low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 register name: crt_cur_locl start vertical sync register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 register name: crt_vsync_st end vertical sync register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 register name: crt_vsync_end vertical display end register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 register name: crt_vdsp_end offset register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 register name: crt_offset underline register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 register name: crt_underline start vertical blank register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 register name: crt_vblank_st end vertical blank register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 register name: crt_vblank_end t able of c ontents btv2115 brook t ree viii bt mode control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 register name: crt_mode_ctl line compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 register name: crt_linecmp vga attribute controller (i/o mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 attribute index and data port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 register name: att_addr read data port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 register name: att_rd palette registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 register name: att_pal_reg[15:0] mode control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 register name: att_mode overscan color register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 register name: att_ovrs color plane enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 register name: att_cpe horizontal panning register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 register name: att_hpan color select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 register name: att_clrsel vga general / external registers (i/o mapped) . . . . . . . . . . . . . . . . . . . . . . . . 84 pos102 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 register name: mca_pos adapter sleep register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 register name: adapt_sleep motherboard sleep register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 register name: mbd_sleep input status #0 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 register name: inp_stat0 color input status #1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 register name: inp_stat_c monochrome input status #1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 register name: inp_stat_m write miscellaneous output register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 register name: misc_out_w read miscellaneous output register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 register name: misc_out_r feature control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 register name: fc vga color registers (i/o mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 dac mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 register name: dac_mask dac state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 register name: dac_state t able of c ontents btv2115 brook t ree ix bt dac read address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 register name: dac_rdaddr dac write address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 register name: dac_wraddr dac data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 register name: dac_data legacy audio fm registers (i/o mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 opl bank 0 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 register name: adlib_bnk0_addr register name: opl3_bnk0_addr2 register name: opl2_bnk_addr2 register name: opl3_bnk0_addr4 register name: opl2_bnk_addr4 opl bank 0 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 register name: opl3_bnk0_data2 register name: opl2_bnk_data2 register name: opl3_bnk0_data4 register name: opl2_bnk_data4 opl bank 1 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 register name: adlib_bnk1_addr register name: opl3_bnk1_addr2 register name: opl3_bnk1_addr4 opl bank 1 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 register name: adlib_bnk1_data register name: opl3_bnk1_data2 register name: opl3_bnk1_data4 legacy audio mixer registers (i/o mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . 94 mixer address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 register name: la_mix_addr2 register name: la_mix_addr4 mixer data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 register name: la_mix_data2 register name: la_mix_data4 legacy audio dsp registers (i/o mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 dsp reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 register name: la_dsp_reset2 register name: la_dsp_reset4 dsp read data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 register name: la_dsp_read2 register name: la_dsp_read4 dsp command-data / command status . . . . . . . . . . . . . . . . . . . . . . . . . . 95 register name: la_dsp_cmd2 register name: la_dsp_cmd4 t able of c ontents btv2115 brook t ree x bt dsp read status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 register name: la_ready2 register name: la_ready4 audio registers (memory mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 gui aperture registers (memory mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 gui accelerator registers (memory mapped) . . . . . . . . . . . . . . . . . . . . . . . . . 96 video input registers (memory mapped) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 cpu address space apertures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 protected mode aperture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 direct map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 flippin map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 funky map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 funky map support for sev . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 gui command/register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 gui fifo register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 register name: guireg_fifo gui fifo depth register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 register name: guireg_depth flash rom support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 yamaha support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 audio subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 gui base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 register name: grp_gui_base[3:0] mba control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 register name: guireg_mba real mode aperture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 vga rom aperture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 cpu apertures in a pci-bus environment . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 pm_base field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 prefetch base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 pci constraints on gbase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 t able of c ontents btv2115 brook t ree xi bt con?uration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 register initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 i 2 c master and slave controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 i 2 c control write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 register name: grp_i2c_ctrlw i 2 c control read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 register name: grp_i2c_ctrlr i 2 c master module software interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 i 2 c master data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 register name: grp_i2c_mdata i 2 c master control read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 register name: grp_i2c_mctrlr i 2 c master control write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 register name: grp_i2c_mctrlw i 2 c slave module software interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 i 2 c slave data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 register name: grp_i2c_sdata i 2 c slave control read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 register name: grp_i2c_sctrlr i 2 c slave control write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 register name: grp_i2c_sctrlw gui accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 gui theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 retained bitmap context. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 raster operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 cpu addressing of gui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 gui commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 rwregister command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 bitblt command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 rwguidata command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 line draw command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 stretchblt command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 t able of c ontents btv2115 brook t ree xii bt gui registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 bitmap context registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 gui con?uration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 register name: guireg_cfg foreground color register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 register name: gui_fg_color background color register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 register name: gui_bg_color destination xy increment register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 register name: gui_dest_xy_inc blt control register (direction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 register name: gui_blt_control line control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 register name: gui_line_control line pattern register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 register name: gui_line_pattern bresenham 0, address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 register name: gui_bres0_addr bresenham 0, error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 register name: gui_bres0_err bresenham 0, k1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 register name: gui_bres0_k1 bresenham 0, k2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 register name: gui_bres0_k2 bresenham 0, increment 1 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 register name: gui_bres0_inc1 bresenham 0, increment 2 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 register name: gui_bres0_inc2 bresenham 0, length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 register name: gui_bres0_length software encoded video (sev) player . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 organization of display data in memory . . . . . . . . . . . . . . . . . . . . . . . . . . 185 limitations on the display data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 programming the sev block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 sev controller write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 register name: grp_sv_ctrlw[3:0] sev controller read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 register name: grp_sv_ctrlr[3:0] accessing sev registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 t able of c ontents btv2115 brook t ree xiii bt pacdac controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 pacdac data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 master structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 packet ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 graphics data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 cursor data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 video data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 timing structure data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 dac data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 sample master structure setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 cpu host bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 vesa local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 vl address bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 vl byte enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 vl data bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 vl address strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 vl reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 vl clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 vl memory or io status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 vl data or code status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 vl read or write status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 vl identi?r pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 vl ready return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 vl local device select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 vl local ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 interrupt request line 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 vl bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 pci bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 pci address and data bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 pci bus command and byte enables. . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 pci parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 pci clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 pci reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 pci cycle frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 pci initiator ready. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 pci target ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 pci stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 pci initialization device select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 t able of c ontents btv2115 brook t ree xiv bt pci device select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 pci interrupt a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 pci high speed read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 pci con?uration space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 pci vendor id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 register name: pci_vendor_id pci device id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 register name: pci_device_id pci command registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 register name: pci_command0, pci_command1 pci status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 register name: pci_status pci revision id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 register name: pci_revision_id pci class code registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 register name: pci_class0_id, pci_class1_id pci base address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 register name: pci_base0_reg, pci_base1_reg pci prefetchable base address registers. . . . . . . . . . . . . . . . . . . . . . . . . 222 register name: pci_pref_base0, pci_pref_base1 pci rom base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 register name: pci_rom_base0, pci_rom_base1 pci interrupt line register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 register name: pci_int_line[7:0] pci interrupt pin register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 register name: pci_int0_pin, pci_int1_pin video ram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 vram signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 vram con?urability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 vram types supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 vram parallel data cycle types supported . . . . . . . . . . . . . . . . . . . . . . . . . . 231 refresh cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 dram read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 dram write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 load color register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 dram non-masked block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 register transfer (dram to sam). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 page mode cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 vram timing considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 t able of c ontents btv2115 brook t ree xv bt non-vram attachment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 rom con?urability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 rom connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 rom read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 flash rom write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 yamaha con?urability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 yamaha fm synthesizer connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 video input subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 buffer management hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 video control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 register name: aud_vcr video one register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 register name: aud_v1r video two register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 register name: aud_v2r video address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 register name: var init structure de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 capture control structure de?ition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 line numbering system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 live video input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 closed captioning capture with a video icon . . . . . . . . . . . . . . . . . . . . . . . 264 single frame record example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 parallel decoder interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 signal de?itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 video interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 aes/ebu format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 aes references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 audio subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 audio data formats in the media buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 283 t able of c ontents btv2115 brook t ree xvi bt audio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 register name: aud_isr interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 register name: aud_imr interrupt state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 register name: aud_istr application port read data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 register name: aud_appr btv2300 chip id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 register name: aud_cid serial data control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 register name: aud_sdcr encoder block length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 register name: aud_ebl encoder block position register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 register name: aud_ebp decoder status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 register name: aid_dsr reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 register name: reserved channel status byte 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 register name: aud_ch0 channel status byte 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 register name: aud_ch1 channel status byte 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 register name: aud_ch2 channel status byte 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 register name: aud_ch3 reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 register name: reserved primary stream address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 register name: aud_psa primary stream counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 register name: aud_psc secondary stream address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 register name: aud_ssa secondary stream counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 register name: aud_ssc level registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 primary level registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 register name: aud_pll, aud_prl secondary level registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 register name: aud_sll, aud_srl record monitoring level registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 register name: aud_rmll, aud_rmrl t able of c ontents btv2115 brook t ree xvii bt number summed register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 register name: aud_ns[1:0] right/left playback sum registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 register name: aud_lpsum, aud_rpsum right/left playback max registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 register name: aud_lpmax, aud_rpmax right/left record sum registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 register name: aud_lrsum, aud_rrsum right/left record max registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 register name: aud_lrmax, aud_rrmax legacy audio emulation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 register name: la_emulation_registers btv2300 address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 register name: aud_car btv2300 register shadows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 register name: aud_clk filter clock divisor register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 register name: aud_fclk codec mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 register name: aud_cmode application port direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 register name: aud_appo application port write data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 register name: aud_appd btv2300 mixer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 register name: aud_mix btv2300 mux selector register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 register name: aud_mux cd left attenuation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 register name: aud_cdl cd right attenuation register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 register name: aud_cdr line left attenuation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 register name: aud_ll line right attenuation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 register name: aud_lr fm left attenuation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 register name: aud_fml fm right attenuation register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 register name: aud_fmr mic left gain register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 register name: aud_micl mic right gain register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 register name: aud_micr t able of c ontents btv2115 brook t ree xviii bt dac left attenuation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 register name: aud_dacl dac right attenuation register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 register name: aud_dacr channel status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 operating speci?ations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 vram timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 btv2115 subsystem vram load limits . . . . . . . . . . . . . . . . . . . . . . . . . . 323 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 target dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 target ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 package power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 packaging speci?ations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 btv2115 vl-bus pin layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 btv2115 pci-bus pin layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 l ist of f igures btv2115 brook t ree xix bt l ist of f igures figure 1. btv configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 2. btv2115 vl-bus block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. btv2115 pci-bus block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. cpu apertures on a vl system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 5. cpu apertures on a pci system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 6. hbus agents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 7. protected mode aperture mapping to vram . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 8. media buffer access via direct map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 9. protected mode aperture accessing vram via flippin map . . . . . . . . . . . . . . 106 figure 10. funky map sev. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 11. non-queued, queued and vram queued gui interface . . . . . . . . . . . . . . . . . 115 figure 12. gui command/register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 13. flash rom access address mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 figure 14. yamaha access address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 15. audio access address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 16. configuration resistor straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 17. configuration registers and strapping bits for btv2115. . . . . . . . . . . . . . . . . . 136 figure 18. queued gui address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 19. non-queued gui address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 20. organization of display data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 21. accessing sev registers through vga extension bus . . . . . . . . . . . . . . . . . . 193 figure 22. vl_clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 figure 23. vl_ads and vl_ldev timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 figure 24. vl_lrdy delay timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 figure 25. data timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 figure 26. pci con?uration space header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 figure 27. vram refresh cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 figure 28. vram read cycle (80ns cycle timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 figure 29. vram read cycle (70ns cycle timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 figure 30. vram read cycle (60ns cycle timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 figure 31. dram masked write cycle (80ns cycle timing) . . . . . . . . . . . . . . . . . . . . . . . . 235 figure 32. dram masked write cycle (70ns cycle timing) . . . . . . . . . . . . . . . . . . . . . . . . 236 figure 33. dram write cycle (60ns cycle timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 34. load color register cycle (all speeds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 figure 35. dram non-masked block write cycle (80ns cycle timing) . . . . . . . . . . . . . . . 239 figure 36. dram non-masked block write cycle (70ns cycle timing) . . . . . . . . . . . . . . . 240 l ist of f igures btv2115 brook t ree xx bt figure 37. dram non-masked block write cycle (60ns cycle timing). . . . . . . . . . . . . . . . 241 figure 38. dram memory-to-register transfer cycle (80ns cycle timing) . . . . . . . . . . . . 242 figure 39. vram memory-to-register transfer cycle (70ns cycle timing) . . . . . . . . . . . . 243 figure 40. vram memory-to-register transfer cycle (60ns cycle timing) . . . . . . . . . . . . 244 figure 41. page mode cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 figure 42. rom connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 figure 43. rom read cycle (70ns part). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 figure 44. rom read cycle (120ns part). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 figure 45. flash rom write cycle (70ns part) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 figure 46. flash rom write cycle (120ns part) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 figure 47. btv2115 connections to yamaha fm synthesizer . . . . . . . . . . . . . . . . . . . . . . 252 figure 48. video input subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 figure 49. video input control structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 figure 50. video input subsystem block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 figure 51. reference signals for scaling window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 figure 52. video interface timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 figure 53. typical audio system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 figure 54. aes framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 figure 55. aes timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 figure 56. btv2115 audio subsystem block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 figure 57. audio processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 figure 58. stream and data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 figure 59. worst case power dissipation for power quad . . . . . . . . . . . . . . . . . . . . . . . . 331 figure 60. worst case power dissipation for heat spreader mqfp . . . . . . . . . . . . . . . . . 332 figure 61. vram read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 figure 62. vram masked write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 figure 63. load color register cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 figure 64. cas-before-ras refresh cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 figure 65. vram non-masked block write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 figure 66. vram memory-to-shift register transfer cycle . . . . . . . . . . . . . . . . . . . . . . . . 336 figure 67. page mode cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 figure 68. rom read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 figure 69. rom write cycle, flash rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 figure 70. opl read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 figure 71. opl write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 figure 72. pacdac controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 figure 73. btv2115ksf packaging diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 figure 74. BTV2115AHF packaging diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 figure 75. vl-bus pin layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 figure 76. pci-bus pin layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 l ist of t ables btv2115 brook t ree xxi bt l ist of t ables table 1. btv2115 vl-bus pin list summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 2. btv2115 pci-bus pin list summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. vga modified fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 4. dac register offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5. recommended master structure fields. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6. typical dac structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7. btv2115 i/o address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 8. set/reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 9. enable set/reset register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 10. color compare register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 11. data rotate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 12. read map select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13. mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14. graphics controller: miscellaneous register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15. color don? care register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 16. bit mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 17. pll 25mhz and 28mhz select registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 18. grp_pdac registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 19. configuration register <7> (grp_cfg7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 20. configuration register <6> (grp_cfg6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 21. configuration register <5> (grp_cfg5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 22. configuration register <4> (grp_cfg4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 23. configuration register <3> (grp_cfg3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 24. configuration register <2> (grp_cfg2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 25. configuration register <1> (grp_cfg1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 26. configuration register <0> (grp_cfg0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 27. master structures a and b address registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 28. pacdac controller status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 29. pacdac controller control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 30. read pci prefetch base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 31. read pci rom base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 32. read pci enable registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 33. clocking mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 34. shift & load control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 35. map mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 36. character map select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 l ist of t ables btv2115 brook t ree xxii bt table 37. secondary font selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 38. primary font selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 39. memory mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 40. sequencer unlock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 41. end horizontal blank register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 42. end horizontal sync register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 43. overflow register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 44. preset row scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 45. character height register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 46. cursor start register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 47. cursor end register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 48. end vertical sync register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 49. underline register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 50. mode control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 51. attribute index/data port register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 52. read data port register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 53. palette registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 54. mode control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 55. color plane enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 56. horizontal panning register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 57. allowable pixel pans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 58. color select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 59. pos102 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 60. adapter sleep register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 61. motherboard sleep register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 62. input status #0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 63. input status #1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 64. miscellaneous output register (read and write) . . . . . . . . . . . . . . . . . . . . . . . . 88 table 65. color registers: dac state register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 66. legacy audio fm register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 67. write u/v ([22:21]=00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 68. composite plus ([22:21]=01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 69. write composite index ([22:21]=10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 70. composite minus ([22:21]=11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 71. quadrature modulator cpu bus example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 72. gui fifo register (guireg_fifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 73. gui fifo depth register (guireg_depth) . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 74. submap read/write characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 75. grp_gui_base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 76. gui mba control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 77. bus type encode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 l ist of t ables btv2115 brook t ree xxiii bt table 78. chip model coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 79. grp_i2c_ctrlw control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 80. grp_i2c_ctrlr control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 81. i 2 c master receive data grp_i2c_mdata. . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 82. i 2 c master read control register grp_i2c_mctrlr . . . . . . . . . . . . . . . . . . 142 table 83. grp_i2c_mctrlr current bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 84. example of reading grp_i2c_mctrlr register . . . . . . . . . . . . . . . . . . . . . . 144 table 85. i 2 c master write control register grp_i2c_mctrlw . . . . . . . . . . . . . . . . . . 145 table 86. example of writing to grp_i2c_mctrlw . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 87. i 2 c slave receive data grp_i2c_sdata . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 88. i 2 c slave read control register grp_i2c_sctrlr. . . . . . . . . . . . . . . . . . . . 152 table 89. grp_i2c_sctrlr current bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 90. examples of reading grp_i2c_sctrlr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 91. i 2 c slave write control register grp_i2c_sctrlw . . . . . . . . . . . . . . . . . . . 155 table 92. example of writing to grp_i2c_sctrlw . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 93. address fields for gui accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 table 94. gui commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 95. blt command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 96. xy address format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 97. rwguidata command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 98. rwguidata_length. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 99. line command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 100. stretchblt command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 101. gui registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 102. bitmap context registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 103. bitmap register type field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 104. bitmap register offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 105. bitmap register pitch field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 106. example bitmap context register allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 107. gui configuration register (guireg_cfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 108. foreground color register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 109. background color register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 110. destination xy increment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 111. blt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 112. line control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 113. bresenham 0, address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 114. bresenham 0, error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 115. bresenham 0, constant k1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 116. bresenham 0, constant k2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 117. bresenham 0, increment 1 and 2 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 118. bresenham 0 length register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 l ist of t ables btv2115 brook t ree xxiv bt table 119. page table entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 120. sev grp_sv_ctrlw register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 121. packet size used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 122. sev grp_sv_ctrlr register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 123. pt[3:0] data type assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 124. master structure entry format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 125. up_mode bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 table 126. timing atom bit definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 table 127. timing structure format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 table 128. vl-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 table 129. pci command register - function 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 130. pci command register - function 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 table 131. pci status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 132. pci class code register - function 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 table 133. pci class code register - function 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 134. pci base register - function 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 table 135. pci prefetch base register - function 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 136. pci rom base register - function 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 table 137. vram dual we/dual cas modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 table 138. vram bus signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 table 139. supported vram types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 table 140. flash rom types supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 table 141. video control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 table 142. video one register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 table 143. video two register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 table 144. video address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 table 145. init structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 table 146. capture control structure dword0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 table 147. capture control structure dword1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 table 148. capture control structure dword2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 table 149. parallel decoder interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 table 150. btv2300 register to aux mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 table 151. audio structure dword 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 table 152. audio structure dword 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 table 153. 16-bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 table 154. 8-bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 table 155. 4-bit adpcm format with reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 table 156. 4-bit adpcm format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 table 157. 2.6-bit adpcm format with reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 table 158. 2.6-bit adpcm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 table 159. 2-bit adpcm format with reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 l ist of t ables btv2115 brook t ree xxv bt table 160. 2-bit adpcm format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 table 161. vucb only format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 table 162. aux+vucb format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 table 163. data+aux+vucb format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 table 164. audio address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 table 165. interrupt status, state and mask register bits . . . . . . . . . . . . . . . . . . . . . . . . . 291 table 166. aud_cid btv2300 chip id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 table 167. serial data control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 table 168. decoder status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 table 169. primary address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 table 170. primary stream counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 table 171. secondary address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 table 172. secondary stream counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 table 173. level register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 table 174. primary level registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 table 175. secondary level registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 table 176. record monitoring levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 table 177. number summed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 table 178. playback sum registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 table 179. playback max registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 table 180. record sum registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 table 181. record max registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 table 182. clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 table 183. sample rate examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 table 184. filter clock divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 table 185. codec mode register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 table 186. btv2300 mixer control register shadow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 table 187. btv2300 mux selector register shadow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 table 188. cd left attenuation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 table 189. cd right attenuation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 table 190. line input left attenuation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 table 191. line input right attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 table 192. fm synthesis input left attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 table 193. fm synthesis input right attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 table 194. mic input left gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 table 195. mic input right gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 table 196. dac synthesis input left attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 table 197. dac synthesis input right attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 table 198. channel status usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 table 199. btv2115 output speci?ations for dram signals . . . . . . . . . . . . . . . . . . . . . . . 317 table 200. btv2115 load limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 l ist of t ables btv2115 brook t ree xxvi bt table 201. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 table 202. recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 table 203. target dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 table 204. dc characteristics for iic_sda and iic_scl i/o (fast mode) . . . . . . . . . . . . . 326 table 205. dc characteristics for ddc_sda and ddc_scl i/o (standard mode) . . . . . . 327 table 206. ac characteristics for iic_sda and iic_scl bus lines (fast mode) . . . . . . . . 328 table 207. ac characteristics for ddc_sda and ddc_scl bus lines (standard mode) . 328 table 208. package thermal resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 table 209. btv2115 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 brook t ree xxvii bt p reface what this document contains this hardware speci?ation contains the following chapters. product description ?provides an overview of the btv2115 mediastream con- troller, including a summary of the pci and vl pin assignments. for a summary of the btv mediastream family of chips, refer to the beginning of this technical reference binder. vga implementation ?contains a description of the compatibility and opera- tion of the vga within the btv2115 controller. register de?itions ?contains the de?itions of or references to all of the btv2115 registers, including both i/o mapped and memory mapped reg- isters. cpu address space apertures ?describes the programming interface to the btv2115 mediastream accelerator, the media buffer, the audio sub- system, the ?sh rom, and the yamaha 2 and 4 operator mode fm syn- thesizer family. con?uration registers ?contains a summary of the registers that specify op- erating parameters for interaction of internal and external multimedia sub- system components. i 2 c master and slave controllers ?speci?s the programming interface be- tween the btv2115 and the i 2 c master and slave modules. gui accelerator ?describes the cpu addressing to the gui and de?es the gui commands registers. softvideo player ?describes the interface between the btv2115 software encod- ed video module and the btv2487 pacdac via the vram serial port. cpu host bus interface ?describes the vesa local bus and pci bus interface between the btv2115 and the host cpu. de?es the vesa and pci sig- nal pins and provides timing diagrams. p reface what this document contains btv2115 brook t ree xxviii bt video ram interface ?describes the interface between the btv2115 and the vram bus which provides access to rom, fm synthesizer, and multi- media data and control information. includes timing diagrams and con- nection diagrams. video input subsystem ?describes the interfaces between the btv2115 and the btv2811a videostream decoder, and between the btv2115 and the memory controller and vram via the memory bus. audio interface ?describes the interface between the btv2115 and the audiostream subsystem. operating speci?ations ?provides the operating speci?ations for the btv2115, including electrical, thermal, packaging, and signal pin layout. p reface related documents btv2115 brook t ree xxix bt related documents btv2300 audiostream specification btv2811a videostream decoder specification btv2487 pacdac specification pci local bus specification, revision 2.0 video electronics standards association (vesa) local bus specification, version 2.0 yamaha ymf-262 product information bulletin philips semiconductor, data sheet saa7194, digital video decoder and scalar circuit (desc) philips i 2 c-bus and how to use it access.bus specification - version 2.0 richard f. ferraro, programmer? guide to the ega and vga cards , second edition (addison-wesley publishing company, inc., 1990) bradley dyck kliewer, ega/vga: a programmer? reference guide (intertext publications, mcgraw-hill publishing company, new york, 1990) p reface notation conventions btv2115 brook t ree xxx bt notation conventions notation conventions used in this book are listed below. example description vl_reset the overbar above a signal or pin (or a portion of the signal or pin) indicates active-low. 8?ad hexadecimal notation used by hardware designers, in the format: < num bits>? brook t ree 1 bt p roduct d escription introduction the btv2115 mediastream controller is designed speci?ally for low-cost, high- performance, high-resolution color graphics applications. it is designed to work with the btv2487 pacdac, the btv2300 audiostream interface, and the btv2811a videostream decoder in a high function multimedia user interface subsystem. the complete btv mediastream con?uration is depicted in figure 1 and con- sists of the following major components. btv2115 mediastream controller btv2300 audiostream interface providing stereo audio btv2487 pacdac providing a video cache for vfw acceleration and ntsc/pal output btv2811a videostream decoder providing live video windows p roduct d escription introduction btv2115 brook t ree 2 bt the clock-quadrupled mediastream controller offers very high performance gui acceleration in a very compact form factor. a btv2115 graphics subsystem can be constructed from as little as two vrams, one btv2115, and one btv2487. such a one megabyte con?uration can support 640x480x24 through 1280x1024x4. the 208 pin pqfp package allows glueless attachment to both 32 bit pci ? bus and the vesa ? local bus. the vl ? address bus is fully decoded and demultiplexed, allowing the fastest vl bus cycles. the vram gui fifo can buffer up to 8192 commands permitting essentially full overlap of application and gui command execution. this is the ideal graphics accelerator for medium to high performance motherboards. this same four part con?uration can support two accelerated video windows. decompression acceleration allows 30 frames per second at full screen resolution for software decompressors. this con?uration also supports two cd quality ste- reo output streams with on-chip audio decompression acceleration. the btv2115/ btv2487 system is the ideal graphics and multimedia system for video for win- dows ? applications and is small enough and inexpensive enough for mother- figure 1. btv con?uration btv2115?/v btv2487 pacdac pci or vl bus 32 32 controller btv2811a decoder i 2 c bus rgb ntsc/pal video for windows btv2300 media buffer access.bus (30 fps) vesa ddc software aes dat audiostream interface videostream vcr mediastream encoded fastick btv2210 game port p roduct d escription introduction btv2115 brook t ree 3 bt boards. the btv2115/btv2487 system also supports a software encoded ntsc/ pal video output which can be run in parallel with rgb monitor refresh. the btv2811a single chip ntsc/pal decoder can be gluelessly attached to the btv2115 to turn the two video window system into an ideal platform for video teleconferencing. the video codec acceleration features in the btv2115 allow software compressors and decompressors to function at much higher frame rates. the btv2115 controller is the ?st audio product designed for the pc environ- ment that offers professional quality digital serial audio input and output. the btv2115 and btv2300 provide a completely self-contained windows audio sub- system. in addition, the chip set supports attachment to professional and consumer grade digital audio equipment, such as digital audio tape and digital mini disk units via aes/spdif or cp-340 interfaces with full program access to the aes channel and user data streams. plus, the chip set can receive source material and master digital data streams. these features allow sophisticated, lossless, multipass, off- line edit of audio streams. the btv2115 provides access to the digital subcode data which includes professional time code information, sample rate, etc. on a cd unit, the subcode conveys such information as track position, catalog, pre-empha- sis, etc. the btv2115/btv2300 support simultaneous play and record under mi- crosoft windows ? . in addition, the chip set supports simultaneous play of two stereo streams so that application audio can be digitally mixed with windows sys- tem sounds. also, external audio (analog or digital) can be digitally mixed with the windows playback audio streams so that application audio can be heard through the current background music selection. sophisticated audio metering is provided in hardware for measuring average level, peak level and for detecting clipping in both playback and record. in addition, the btv2115 provides legacy audiopro emulation of the sound hardware normally used to support ms-dos ? based games. legacy audiopro emulation has been designed to work with most popular dos games and is the ?st pci-based product to do so. all other implementations in the market today require isa ? bus attachment. the btv2115 provides decode and bus attachment support for the yamaha ? 2 and 4 operator modes fm synthesizer family. the btv2115 provides a glueless attachment for the optional btv2210 fastick game port controller (refer to the btv2210 game port/midi controller spec ). this combination offers compatibility with today s analog pc joysticks and provides a very high speed digital interface to analog joysticks used in windows 95 ? gaming. the serial bus controlling the btv2487 and btv2811a is i 2 c compatible and available for controlling peripherals such as an add-in tuner and for querying mon- itor characteristics from a suitably equipped monitor, as well as for access.bus ? access to keyboards, mouse and other peripherals. the btv2115 supports monitors equipped with all current vesa display data channel (ddc) modes, including ddc1, ddc2a, and ddc2b. for monitors with ddc2b support, the btv2115 provides access.bus support over the vga monitor cable. the access.bus can be easily switched to a second access.bus port for older style monitors with- out ddc2b support. the btv2115/btv2487 chip set supports the vesa display p roduct d escription introduction btv2115 brook t ree 4 bt power management signalling protocol for controlling monitor power consump- tion on suitably equipped monitors. the btv2115 s maximum frame buffer size is 4mb. two megabytes brings 1024x768x16 and 1280x1024x8 capability to a btv2487-based system. the btv2115 can support up to 1280x1024x16 and 1024x768x24 for vram con?u- rations of greater than 2mb. use of such standard interfaces as vl, pci, aes/ebu, i 2 c, and access.bus greatly simpli?s the system designer s task and offers many interesting opportu- nities for product differentiation. figure 2 presents a block diagram of the vl-bus ? btv2115 con?uration. figure 3 presents a block diagram of the pci-bus ? btv2115 con?uration. p roduct d escription introduction btv2115 brook t ree 5 bt figure 2. btv2115 vl-bus block diagram mdata vl b us i nterface h ost b us c lock g en 100 mh z 50 mh z clk25 m emory b us vga v ideo mm_data mm_clk i 2 c maddr m edia b uffer gui a ccel . a udio pacdac s erial c lock c ontrol sclk pt[3:0] t est tm [2:0] trg bios_cs lsync vrdy lclk[1:0] vl_data vl_addr 30 32 vl_be vl_clock vl_m_io 4 vl_ads vl_lrdy vl_id2 vl_ldev vl_rdyrtn sa_in irq9 opl_cs m emory c ontroller i nterface opl_irq audclk_out soe clk17 aes_out vl_w_r iic_scl iic_sda ddc_scl ddc_sda i nput a ccess m emory c ontrol s ignals [9:0] s ee n ote 1. note 1. refer to table 1 on page 13, column ?ram interface pins?for details on the ras, we, and cas memory control pins. vl_d_c vl_reset sa_out 3 8 dsf 32 9 2 4 4 4 4 2 s oftware e ncoded v ideo o utput c ontrol p roduct d escription introduction btv2115 brook t ree 6 bt figure 3. btv2115 pci-bus block diagram note 1. refer to table 2 on page 17, column ?ram interface pins?for details on the ras, we, and cas memory control pins. mdata pci b us i nterface h ost b us c lock g en 100 mh z 50 mh z clk25 m emory b us vga v ideo mm_data mm_clk i 2 c maddr m edia b uffer gui a ccel . a udio pacdac s erial c lock c ontrol sclk pt[3:0] t est tm [2:0] trg bios_cs lsync vrdy lclk[1:0] pci_ad pci_idsel 32 c_be pci_clk pci_stop 4 pci_par pci_devsel pci_trdy pci_inta sa_in opl_cs m emory c ontroller i nterface opl_irq audclk_out soe clk17 aes_out hs_read iic_scl iic_sda ddc_scl ddc_sda i nput a ccess m emory c ontrol s ignals [9:0] s ee n ote 1. pci_frame pci_rst sa_out 3 24 dsf 32 9 2 4 4 4 4 2 pci_irdy s oftware e ncoded v ideo o utput c ontrol p roduct d escription interface description btv2115 brook t ree 7 bt interface description the btv2115 provides seven interfaces to the graphics subsystem: cpu or host bus interface vram interface pacdac ? interface btv2811a/multimedia interface ? 2 c interface serial audio interface test interface these interfaces are described brie? here; however, for more detail refer to subsequent chapters of this document. cpu/host interface the interface between the cpu and btv2115 is via a vl-32 or pci bus. the actual bus or protocol in use is selected by con?uration strapping resistors on the vram data bus, see below. the vl-32 bus is fully decoded and fully demulti- plexed and provides a glueless vl-slave interface that runs as fast as the vesa vl spec permits. the pci bus interface uses only 46 pins (60% of vl-32). the vl- 32 pins are rede?ed to provide a pci bus interface when the con?uration resis- tors are suitably strapped. the pci interface is compliant with pci speci?ations as of revision 2.0. the vl-32 interface is compliant with version 2.0 of the vesa speci?ation. for more information refer to ?pu host bus interface?on page 211. the btv2115 does not support vl-16 (e.g. 386 microprocessors), eisa , isa, or mca buses. vram interface the vram interface of btv2115 supports many different form factors and speed grades of vram, including ti256kx16 in 70ns and 60ns speed grades as well as various two megabit vrams, (refer to the ?ideo ram interface? starting on page 225 and ?ram timing parameters?on page 317 for complete details). the vram interface supports up to four megabytes of vram. special vram fea- tures are utilized to optimize performance, e.g. nonpersistent write, block write, etc. the vram data bus is used to support additional graphics/multimedia sub- system components like flash rom devices and a yamaha 2 or 4 operator mode fm synthesizer chip. p roduct d escription interface description btv2115 brook t ree 8 bt pacdac interface the pacdac interface is derived internally from the serial clock controller. the sev out, and crt controller all share the serial clock controller to drive the pac- dac. this interface includes the vram serial clocks, vram serial output en- ables, pacdac tag lines and synchronization signals. for more information refer to ?acdac controller?on page 195. multimedia interface the btv2811a videostream decoder chip attaches to btv2115 via the multime- dia interface. all transfers are packetized over an eight bit bus. for pci bus con- ?urations, a 24bit parallel decoder interface for 16 bit ycrcb video data is available in addition to the btv2811a. for details on parallel interface, refer to ?arallel decoder interface?on page 266. i 2 c interface btv2115 contains support for two i 2 c interfaces. either one can be used to support the access.bus protocol. one interface is intended to support vesa ddc1, ddc2a, and ddc2b monitor signal protocols. the other is intended to support communication with the btv2487 and btv2811a even if an older monitor without ddc signalling is attached to the vga connector. for more information refer to ? 2 c master and slave controllers?on page 137. serial audio interface audio i/o to or from the btv2300 is transferred via the aes/ebu format on the serial audio in and serial audio output pins. this interface transfers a serial stereo bit stream at up to 48khz in both directions. the aes_out pin provides an iso- lated version of the serial audio stream for consumer audio equipment access. for more information refer to ?udio interface?on page 271. test interface the test interface includes the test mode pins tm [2:0] and the audclk_out pin. in addition, scan data is shifted into the mm_data[7:0] lines and out the lower eight bits of the maddr lines. p roduct d escription distinguishing features btv2115 brook t ree 9 bt distinguishing features the btv2115 provides the following features. local bus graphics controller (glueless for): - pci 2.0 bus - vesa vl 2.0 bus (32 bit) 32 bit vram (1mb to 4mb) - samsung ? 256kx8: -8,-7,-6 - hitachi ? 256kx8:-8,-7 - texas instruments ? 256kx16:-8,-7,-6 - ibm ? 256kx16:-8,-7,-6 - nec ? 256kx8:-8,-7 up to 1mb of flash rom supports yamaha 2 and 4 operator modes fm synthesizer family resolutions: - 640x480: 4,8,16,24,32 bits/pixel up to 76hz - 800x600: 4,8,16,32 bits/pixel up to 76hz - 1024x768: 4,8,16,24 bits/pixel up to 75hz - 1280x1024: 4,8,16 bits/pixel up to 75hz vga compatibility for modes 00h - 07h and 0dh - 13h multimedia solution - glueless connection btv2811a videostream decoder - acceleration of 2 video windows with hardware double buffering - hardware assisted video playback acceleration - stereo audio in/out - software encoded ntsc/pal video out to vcr - big and little endian support - stretch blt and raster scaling - legacy audiopro ? - digital interface to consumer digital audio tape, minidisc, etc. standard interfaces - pci bus 2.0 compatible - vesa vl bus 2.0 - aes/ebu spdif cp-340 (with full access to channel/user bits) -i 2 c/ access.bus - vesa ddc1, ddc2a/b - vesa dpms p roduct d escription applications and related products btv2115 brook t ree 10 bt applications and related products the btv2115 supports the following applications. microsoft windows ? 3.1, win ?5 ? , and nt ? gui acceleration ibm os/2 ? gui acceleration xwindow system ? acceleration video for windows ? and microsoft windows mpc audio ? high resolution color graphics video-conferencing multimedia applications video playback acceleration the btv related products are as follows. btv2487 pacdac btv2811a videostream decoder btv2300 audiostream interface p roduct d escription btv2115 vl-bus pin list summary btv2115 brook t ree 11 bt btv2115 vl-bus pin list summary below, table 1 provides a summary of the btv2115 pin list for the vl-bus. table 2 provides a summary of the btv2115 pin list for the pci-bus. the overbar above a signal indicates active-low. for a vl-bus pin layout diagram, see figure 75 on page 343. table 1. btv2115 vl-bus pin list summary (1 of 4) pin count signal name i/o description total vl pins = 77 32 vl_data[31:0] io ?l data bus?on page 211 30 vl_addr[31:2] i ?l address bus?on page 211 4 vl_be [3:0] i ?l byte enables?on page 211 1 vl_ads i ?l address strobe?on page 211 1 vl_d_c i ?l data or code status?on page 212 1 vl_m_io i ?l memory or io status?on page 212 1 vl_w_r i ?l read or write status?on page 212 1 vl_clock i vl bus clock (50mhz max). see ?l clock?on page 211 1 vl_reset i ?l reset?on page 211 1 vl_rdyr tn i ?l ready return?on page 212 1 vl_ldev o ?l local device select?on page 212 1 vl_lrdy o ?l local ready?on page 212 1 vl_id2 i ?l identi?r pin?on page 212 1 irq9 o ?nterrupt request line 9?on page 212 p roduct d escription btv2115 vl-bus pin list summary btv2115 brook t ree 12 bt total pacdac and serial controller pins = 15 4 pt[3:0] o pacdac tag to identify data type ?acdac data types?on page 196 4 soe [3:0] o vram serial port serial output enable 2 lclk[1:0] o serial clock to vram, load clock to pacdac 1 lsync i linesync signal from pacdac indicates that btv2115 can begin to load the graphics, video1, video2, cursor and timing fifos. 1 vrdy i sev signal from pacdac indicates that the highwater mark on the sev out fifo has not been reached and that btv2115 might send further sev fifo packets. 1 sclk i serial clock input from pacdac. 1 clk17 i audio clock input from pacdac. 1 clk25 i main clock input from pacdac. from this signal, a 100mhz and a 50mhz clock are derived for the chip core (vga, gui, audio, etc). table 1. btv2115 vl-bus pin list summary (2 of 4) pin count signal name i/o description p roduct d escription btv2115 vl-bus pin list summary btv2115 brook t ree 13 bt total vram interface pins = 57 24 mdata[31:8] i/o bidirectional tri-state vram memory data. due to address line loading and pin limitations, address lines for flash rom and register-selects for yamaha fm synthesizer are multiplexed on mdata[27:8]. 8 mdata[7:0] i/o bidirectional tri-state vram, rom, and yamaha data. 9 maddr[8:0] o multiplexed memory address lines to vram capable of driving up to 8 vrams. in testmode, maddr[7:0] conveys the internal scan chain data out of the chip. 4 ras [3:0] o vram row address strobe (ras), 1 per bank, up to 4mb 1 cas0 o dual cas: vram column address strobe (cas) for the least signi?ant byte of the 32 bit data bus, byte0. dual we: write enable (we ) for byte0. 1 cas1 o dual cas: cas for byte1. dual we: cas for least signi?ant 16 data bits (byte1 and byte0). 1 we0 o dual cas: we for least signi?ant 16 data bits (byte1 and byte0). dual we: write enable (we) for byte1. yamaha and flash rom write pins connected here or identically to we3 1 cas2 o dual cas: vram column address strobe (cas) for byte2. dual we: write enable (we) for byte2. 1 cas3 o dual cas: cas for byte3. dual we: cas for most signi?ant 16 data bits (byte3 and byte2). 1 we1 o dual cas: we for most signi?ant 16 data bits (byte3 and byte2). dual we: write enable (we) for byte3. yamaha and flash rom write pins connected here or identically to we0 1 trg o vram transfer enable, also sampled at ras fall during non-refresh cycles, to select between dram external access or dram to sam reg- ister transfer (sam to dram is not supported by btv2115). trg is also used as read/write for flash rom and yamaha 1 dsf o vram special function select. sampled at ras fall, dsf=0 during refresh cycles resets masked (write-per-bit) mode to non-persistent. during masked writes, dsf must be low (=0). during non-masked writes, dsf=0 selects normal dram, and dsf=0 selects register load. sampled at cas fall of dram cycles, dsf selects block mode. 1 bios_cs o flash rom chip select 1 opl_cs o yamaha fm synthesizer chip select. the synthesizer data bus is attached to vram_data[7:0]. 1 opl_irq i yamaha interrupt input (with an internal pull-up). 1 reset_out o reset to supported peripherals: btv2487, btv2811a, btv2300, yamaha, etc table 1. btv2115 vl-bus pin list summary (3 of 4) pin count signal name i/o description p roduct d escription btv2115 vl-bus pin list summary btv2115 brook t ree 14 bt total serial interface pins = 7 1 aes_out o output to aes compatible consumer electronics (such as dat tape, etc.) 1 sa_out o serial audio output to compatible audio stream interface such as the btv2300. 1 sa_in i serial audio input from the audio adc. this bit serial input supports left and right channel 16 bit input and is asynchronous to mclk. this signal is internally pulled up. 2 iic_scl, iic_sda i/o i 2 c interface pins, used for i 2 c bus. optional for access.bus for pre- ddc monitor 2 ddc_scl, ddc_sda i/o i 2 c interface pins, used for i 2 c bus for support of the vesa ddc1 and ddc2 signalling modes as well as for access.bus when presented through the monitor vga cable, as in vesa ddc2b signalling. total test pins = 4 3tm [2:0] i test mode, signals, 111= normal operation, 000 = tri-state, all outputs. these signals are internally pulled up. 1 audclk_out o audio clock for driving the audiostream interface clock-in. for test pur- poses, the 50mhz internal clock of btv2115 is output when tm [2:0] = 011. when tm [2:0] = 010, a delayed version of the 50mhz internal clock of btv2115 is output. for normal mode (tm [2:0] = 11x), audio clock is output total multimedia bus pins = 9 8 mm_data[7:0] i multimedia data input. in test modes, scan chain inputs enter the chip through these pins. these pins are pulled up internally. 1 mm_clk i multimedia clock, this clock is used to transfer data on the multimedia bus. this pin is pulled up internally total vl-bus signal pins = 169 total non-signal pins = 39 19 gnd ground 17 vdd 5v power supply 1 g_pll ground for internal pll 1 v_pll power for internal pll 1 n_c no connect. pci_inta in pci mode. total btv2115 vl-bus pins = 208 table 1. btv2115 vl-bus pin list summary (4 of 4) pin count signal name i/o description p roduct d escription btv2115 pci-bus pin list summary btv2115 brook t ree 15 bt btv2115 pci-bus pin list summary below, table 2 provides a summary of the btv2115 pin list for the pci-bus. table 1 provides a summary of the btv2115 pin list for the vl-bus. the overbar above a signal indicates active-low. for a pci-bus pin layout diagram, see figure 76 on page 344. table 2. btv2115 pci-bus pin list summary (1 of 4) pin count signal name i/o description total pci pins =47 32 pci_ad[31:0] i/o- 3s ?ci address and data bus?on page 216 4 c_be [3:0] i ?ci bus command and byte enables?on page 217 1 pci_st op i/o- 3s ?ci stop?on page 218 1 pci_p ar o- 3s ?ci parity?on page 217 1 pci_trdy i/o- 3s ?ci target ready?on page 218 1 pci_devsel i/o- 3s ?ci device select?on page 218 1 pci_irdy i ?ci initiator ready?on page 217 1 pci_frame i ?ci cycle frame?on page 217 1 pci_idsel i ?ci initialization device select?on page 218 1 hsread i ?ci high speed read?on page 218 1 pci_int a i/o ?ci interrupt a?on page 218 1 pci_clk i ?ci clock?on page 217 1 pci_rst i ?ci reset?on page 217 p roduct d escription btv2115 pci-bus pin list summary btv2115 brook t ree 16 bt total pacdac and serial controller pins = 15 4 pt[3:0] o pacdac tag 4 soe [3:0] o vram serial port serial output enable 2 lclk[1:0] o serial clock to vram, load clock to pacdac 1 lsync i linesync signal from pacdac indicates that btv2115 can begin to load the graphics, video1, video2, cursor and timing fifos. 1 vrdy i sev signal from pacdac indicates that the highwater mark on the sev out fifo has not been reached and that btv2115 might send further sev fifo packets. 1 sclk i serial clock input from pacdac. 1 clk17 i audio clock input from pacdac. 1 clk25 i main clock input from pacdac. from this signal, a 100mhz and a 50mhz clock are derived for the chip core (vga, gui, audio, etc). total multimedia bus pins =25 8 mm_data[23:16] i a. parallel decoder interface 8 mm_data[15:8] i a. parallel decoder interface, b. chroma[7:0] mode 8 mm_data[7:0] i multimedia data input. in test modes, scan chain inputs enter the chip through these pins. these pins are pulled up internally. a. parallel decoder interface 1 mm_clk i multimedia clock, this clock is used to transfer data on the multimedia bus. this pin is pulled up internally a. to enable parallel decoder interface, refer to bit 2 on table 141 on page 256. b. to enable chroma keying, refer to the chroma_mode ?ld in table 146 on page 259. table 2. btv2115 pci-bus pin list summary (2 of 4) pin count signal name i/o description p roduct d escription btv2115 pci-bus pin list summary btv2115 brook t ree 17 bt total vram interface pins = 57 24 mdata[31:8] i/o bidirectional tri-state vram memory data. due to address line load- ing and pin limitations, address lines for flash rom and register selects for yamaha fm synthesizer are multiplexed on mdata[27:8]. 8 mdata[7:0] i/o bidirectional tri-state vram, rom, and yamaha data. 9 maddr[8:0] o multiplexed memory address lines to vram capable of driving up to 8 vrams. in testmode, maddr[7:0] conveys the internal scan chain data out of the chip. 4 ras [3:0] o vram row address strobe (ras), 1 per bank, up to 4mb 1 cas0 o dual cas: vram column address strobe (cas) for the least signi? cant byte of the 32 bit data bus, byte0. dual we: write enable (we) for byte0. 1 cas1 o dual cas: cas for byte1. dual we: cas for least signi?ant 16 data bits (byte1 and byte0). 1 w_w1e0 o dual cas: we for least signi?ant 16 data bits (byte1 and byte0). dual we: write enable (we) for byte1. yamaha and flash rom write pins connected here or identically to we1 1 cas2 o dual cas: vram column address strobe (cas) for byte2. dual we: write enable (we) for byte2. 1 cas3 o dual cas: cas for byte3. dual we: cas for most signi?ant 16 data bits (byte3 and byte2). 1 we1 o dual cas: we for most signi?ant 16 data bits (byte3 and byte2). dual we: write enable (we) for byte3. yamaha and flash rom write pins connected here or identically to we0 1 trg o vram transfer enable, also sampled at ras fall during non-refresh cycles, to select between dram external access or dram to sam register transfer (sam to dram is not supported by btv2115). trg is also used as read/write for flash rom and yamaha 1 dsf o vram special function select. sampled at ras fall, dsf=0 during refresh cycles resets masked (write-per-bit) mode to non-persistent. during masked writes, dsf must be low (=0). during non-masked writes, dsf=0 selects normal dram, and dsf=0 selects register load. sampled at cas fall of dram cycles, dsf selects block mode. 1 bios_cs o flash rom chip select 1 opl_cs o yamaha fm synthesizer chip select. the synthesizer data bus is attached to vram_data[7:0]. 1 opl_irq i yamaha interrupt input (with an internal pull-up). 1 reset_out o reset to supported peripherals: btv2487, btv2811a, btv2300, yamaha, etc table 2. btv2115 pci-bus pin list summary (3 of 4) pin count signal name i/o description p roduct d escription btv2115 pci-bus pin list summary btv2115 brook t ree 18 bt total serial interface pins = 7 1 aes_out o output to aes compatible consumer electronics (such as dat tape, etc.) 1 sa_out o serial audio output to compatible audio stream interface such as the btv2300. 1 sa_in i serial audio input from the audio adc. this bit serial input supports left and right channel 16 bit input and is asynchronous to mclk. this signal is internally pulled up. 2 iic_scl, iic_sda i/o i 2 c interface pins, used for i 2 c bus. optional for access.bus for pre-ddc monitor 2 ddc_scl, ddc_sda i/o i 2 c interface pins, used for i 2 c bus for support of the vesa ddc1 and ddc2 signalling modes as well as for access.bus when pre- sented through the monitor vga cable, as in vesa ddc2b signal- ling. total test pins = 4 3tm [2:0] i test mode, signals, 111= normal operation, 000 = tri-state, all out- puts. these signals are internally pulled up. 1 audclk_out o audio clock for driving the audiostream interface clock-in. for test purposes, the 50mhz internal clock of btv2115 is output when tm [2:0] = 011. when tm [2:0] = 010, a delayed version of the 50mhz internal clock of btv2115 is output. for normal mode (tm [2:0] = 11x), audio clock is output total pci-bus signal pins = 155 total non-signal pins = 53 19 gnd ground 17 vdd 5v power supply 1 g_pll ground for internal pll 1 v_pll power for internal pll 12 pci_pdn[11:0] i pci pulldown pins 3 pci_nc[2:0] no connect total btv2115 pci-bus pins = 208 table 2. btv2115 pci-bus pin list summary (4 of 4) pin count signal name i/o description brook t ree 19 bt vga i mplementation vga compatibility the btv2115 is fully compatible with vga applications. upon con?uring and enabling the btv2115 vga sub-module, the chip emulates standard vga hard- ware without the aid of software. (for pc platforms, btv-supplied video bios properly initializes the chip for vga operation.) once the chip is con?ured, ap- plications may take full advantage of the vga-de?ed hardware capability and switch vga modes either through bios calls or by programming the vga regis- ter set directly. the btv2115 also supports vesa bios extensions to standard vga modes (super vga modes). however, for super vga, applications must switch modes through bios calls. this is reasonable (and standard practice) since the selection of super vga pixel clock frequencies is non-standard in industry vga imple- mentations. however, in the majority of vesa bios modes, applications can freely program those vga registers which don t determine the basic monitor tim- ing. within a register de?ition, the functional de?ition is implemented for all of the ?lds required for vga compatibility. if the btv2115 does not support a ?ld s functionality that was present in previous vga implementations, it is only because that particular functionality was required by the previous implementation, but not required by current implementations. nevertheless, any software that was written to access that ?ld, may write and read the ?ld as before. the written val- ues are stored in the vga register for later retrieval. the only difference is that value in the register will have no effect on vga operation. an example of such ?lds are the asynchronous reset and synchronous reset bits in the sequencer reset register. vga i mplementation vga operation btv2115 brook t ree 20 bt vga operation this speci?ation does not intend to de?e the vga architecture and functional- ity; application programmers should consult a book on the subject. however, the chapter ?egister de?itions?provides a list of vga registers, including i/o ad- dresses, read/write capability, and a list of the ?lds within that register. simultaneous operation with other btv2115 modules the btv hardware does not preclude the simultaneous operation of the vga and gui or vga and video modules. however, such operations are usually not feasi- ble because vga applications typically do not include a driver-based interface to gui or video functionality. btv2115 assumes that gui and video applications (such as microsoft windows or video for windows) will run with vga hardware disabled, and provides drivers accordingly. a gui application could run in that sit- uation using a standard vga driver, but the gui block would be disabled and only the vga module enabled. whether motion video applications work with a vga graphics driver is a design choice in the coding of the btv2115 low-level video driver. a full-screen dos window within windows can also take advantage of the vga hardware. however, when switching to a full-screen dos window, the gui hardware is again disabled so that gui and vga hardware are not actually en- abled concurrently. the btv product provides hardware, ?mware, and software to run vga appli- cations which access audio hardware through standard i/o locations. vga and pacdac controller the vga de?ition originally assumed that the vga hardware directly drove the monitor timing signals and directly sequenced pixel data to the dac. this was done through a vga sub-module called the crt controller. since the btv2115 instead implements a packet-based interface to a multi-media pacdac device, the btv2115 vga module implemented some unique mechanisms to emulate the vga crt controller functionality. basically, the vga module must generate data structures in the vram media buffer based on the contents of vga i/o reg- isters and the vga memory-mapped frame buffer. the btv2115 pacdac con- troller will then process these data structure to send packets to the pacdac device. the vga frame buffer is stored in a 256kb region starting at address zero of the vram media buffer, and the pacdac data structures are stored at a con?- urable region outside of this 256kb region. here is a brief review of the packet-based architecture. (for more detail consult the chapter ?acdac controller?) rather than sending pixel and monitor control signals to the dac in real time, packets describing the screen are burst to a pac- dac device on a line-by-line basis. the pacdac buffers these packets in fifos, vga i mplementation vga operation btv2115 brook t ree 21 bt and then constructs the scan line on the monitor screen by unloading the contents of these fifos in real time. several packet types are de?ed on the packet bus, but for vga, the important packet types are graphics, timing, and dac register (or i/o) packets. the graphics packets contain the pixel data, the timing packets contain the monitor timing infor- mation, and the dac register packets contain values which will be programmed into con?uration registers in the pacdac device. graphics packets are only sent during scan lines which contain active pixels. timing packet types are sent on every line. they are required to maintain the mon- itor sync timing. they also control when the graphics pixel data is unloaded from the fifo for the active portion of the screen. dac register (or i/o) packet types are sent at the start of every frame during vertical blanking. the vga uses these i/o packets to program the dac palette (based on the vga color registers), the border color (based on the vga attribute overscan register), and the pixel clock rate (based on the miscellaneous output register). consequently, until the cpu writes a new value to either the vga dac color registers, the attribute overscan register, or the pixel clock select ?ld in the mis- cellaneous output register, these packets will program the same values into the pacdac registers at the beginning of every frame. therefore, rather than sending the vga pixels to a standard dac, the vga module must write the pixel data back into the vram media buffer at a location and format expected by the btv2115 pacdac controller. there is a data struc- ture for each packet type: graphics display (the pixel values, which are 8-bit palette indexes for vga), timing, and i/o (or dac register). thus, the vga module is responsible for generating a graphics display structure based on the vga frame buffer contents, generating a timing structure in vram based on the contents of the vga crt registers and sequencer clocking mode register, and generating parts of the dac register structure based on vga color registers, the vga at- tribute overscan register, and the clock select bit of the vga miscellaneous out- put register. there is also a master structure required by the btv2115. the master structure contains generic con?uration information as well as pointers to the other packet- speci? data structures described above. the master structure also contains other ?lds for each packet type which tell it how to send the packets. some of these ?lds depend on the vga mode, and consequently the vga module will modify these ?lds too. these ?lds are shown in table 3. vga i mplementation vga operation btv2115 brook t ree 22 bt once again, the vga frame buffer is always mapped into the ?st 256 kb of the media buffer s addressing space, and the other data structures are stored anywhere else, depending on how the master structure is set up. in turn, the master struc- ture s location depends on the pdc_msptr registers. the vga module initiates writes to the timing structure, dac register data structures, and the master structure only upon detecting modi?ations to the cor- responding vga registers. however, it continually cycles through the vga frame buffer to translate its contents into the graphics data structure the vga reads the master structure to determine where the graphics and timing data structures are to be stored. (it determines where the master structure is located from the pdc_msptr registers.) on the other hand, to determine where to store the dac register values, it reads internal registers, pdac_ptr1 and pdac_ptr0 (see ?ac alias pointer reg- isters?on page 46). this method was chosen over reading the dac register point- er from the master structure because the vga does not generate the whole dac register structure, it just modi?s a part of it. software or bios must build the rest of the dac register structure around the vga-generated data. this register gives the code ?xibility as to where to locate the vga-generated data within the struc- ture. the vga always stores dac register values that it modi?s at ?ed positions relative to the location indicated by the pdac_ptr registers. as shown in table 4, the writes to the dac register structure in the media buffer are triggered by writes to the corresponding vga registers. table 3. vga modi?d fields master structure field purpose gd_x controls the number of graphics packets to send on each line. depends on vga horizontal resolution. gd_y controls which scan lines contain active video. depends on vga vertical display enable, vertical sync start, and vertical total registers. ts_length controls the number of timing atoms in the timing structure. depends on any vga crt register which affects the timing structure, which is most of them. vga i mplementation vga operation btv2115 brook t ree 23 bt see the btv2487 pacdac speci?ation for details about the format of the dac register data for each register type. another important aspect of the interaction between the vga and pacdac controller modules is mode switching. a hardware mechanism allows dynamic mode switching. here, ?ynamic mode switching?means that an application can directly modify the values of the vga crt registers without having to disable the vga module. the mechanism allows the vga module to specify to the pac- dac controller when to switch between the two master structures which are de- ?ed as part of the pacdac controller architecture. this special mechanism is necessary to prevent the crt controller from modifying the structures while the pacdac controller is in the middle of generating the structures. modifying any vga register that affects either the timing structure or master structure would cause a system failure if this mechanism were not implemented. in general, the pacdac controller provides dual master structures to allow mode switching. this allows software (or in this case the vga hardware) to mod- ify one set of structures while the pacdac controller continues to process the ac- tive set. when the modi?ations are done, software (or vga hardware) requests the pacdac controller to switch the active master structure at the end of the cur- rent frame. the vga module is aware of the two master structures. it modi?s the inactive structure (and associated data structures pointed to by the master struc- ture). when done, it asserts an internal hardware signal requesting the pacdac controller to switch the active structure. for this mechanism to work, the timing structure pointer of each master structure (ts_pntr), must be different. all other values in the both master structures can be identical. the algorithm for switching modes is as follows. first, the procedure is kicked off by any modi?ation to any of the bit ?lds which affect either the timing or master structure. the vga regenerates the entire timing structure and the master structure entries listed in table 3, regardless of which bit was modi?d. the ?lds that will kick off a mode switch include bits 3 and 0 of the vga sequencer clock mode register and most of the vga crt registers. the vga module reads the location of the inactive master structure from an internal register. it then reads the timing structure pointer from the master structure itself. next it starts processing the vga registers to generate a new timing structure and some master structure entries. upon completing the modi?ations, the vga module asserts a hardware table 4. dac register offset dac register type offset from pdac_ptr in dwords modi?ation triggered by: dac palette 0-255 palette writes to 3c9 dac data register border color index (overscan) 257 writes to vga attribute overscan register pixel clock pll 258 writes to clock select ?ld of vga miscella- neous output register vga i mplementation vga operation btv2115 brook t ree 24 bt signal which requests that the btv2487 switch master structures at the end of the frame. the vga module keeps track of whether changes to vga crt registers were made while it was generating structures in the media buffer. therefore, no modi? cations will be missed. the crtc continues to generate the inactive structure and the pacdac controller does not switch structures until structure generation com- pletes with no further pending modi?ations. assuming that the software or bios does a series of consecutive writes to vga crt registers, the ?st register modi- ?ation will kick off a mode switching procedure. while this is happening, the vga module sets an internal ?g which indicates that modi?ations are pending. the btv2115 architecture does not require that vga software modify the vga crt registers in any speci? order. intermediate frames may not have the desired monitor timing, but they will not cause system failure. vga i mplementation vga extension registers btv2115 brook t ree 25 bt vga extension registers some btv2115 implementation-speci? register ?lds are unique to the vga. some are provided to con?ure how the vga backend logic writes data structures into the media buffer. other ?lds provide status of the vga modules. these are implementation-speci? registers which are located in the vga graphics control- ler extension space. however, not all registers in that space are related to vga, and hence they are not all listed below. for a complete list of all registers, consult the ?egister de?itions?chapter starting on page 33. the vga ?lds are summarized below. enable vga crt controller mechanism the enable_vga_crtc ?ld in the grp_cfg4 register (bit 2, index 44h) en- ables the vga module to write to any pacdac structure (see table 22 on page 50). if disabled, neither the graphics, timing, or master structure data will be modi?d. if enabled, the enable_vga_crtc_gen bit must also be enabled in order to allow vga generation of the timing structure and parts of the master structure. otherwise, the vga will only generate the graphics data. this bit will not disable access to vga i/o registers or the vga memory-mapped frame buffer. enable vga crt controller structure generation the enable_vga_crtc_gen ?ld in the grp_cfg5 register (bit 7, index 45h) enables the vga module to write the to the timing structure and master structure areas (see table 21 on page 49). this bit is only effective if the enable_vga_crtc bit is set also. when set to zero, this bit allows the vga to run with software-generated timing structures. note that this bit does not disable the generation of the graphics data structure. pacdac pointer the pdac_ptr ?ld in the grp_pdac1 register (bits 2:0, index 27h) and grp_pdac0 register (bits 7:0, index 26h) determines where in the media buffer the vga will store dac register values (see?ac alias pointer registers?on page 46). these registers are mapped into the bits 21:11 of the pointer, so that the pointer can only be set in 2kb increments. the least signi?ant bits are always set to zero. 25 mhz pll select registers grp_25pll1 (index 1bh) and grp_25pll0 (index 1ah) specify the 16-bit pll value to write to the dac register structure when the vga miscella- neous output register is set for a 25 mhz pixel clock. refer to ?ll25 select registers?on page 44. for de?ition of the pll format, see btv2487 pacdac speci?ation . vga i mplementation vga extension registers btv2115 brook t ree 26 bt 28 mhz pll select registers grp_28pll1 (index 1eh) and grp_28pll0 (index 1dh) specify the 16-bit pll value to write to the dac register structure when the vga miscella- neous output register is set for a 28 mhz pixel clock. refer to ?ll28 select registers?on page 45. for de?ition of the pll format, see btv2487 pacdac speci?ation . attribute index status bit 0 of the grp_vgastat register (index 2ch) re?cts the status of the at- tribute register port (see ?ga status register?on page 47). if a zero, writing to 3c0h will write the attribute index register. if a one, writing to 3c0h will write the indexed attribute data register. vga crt generation status when bit 1 of the grp_vgastat register (index 2ch) is set to 1, the vga is busy performing a mode switch. this means it is generating a new timing struc- ture and master structure and when done will request the btv2487 to switch struc- tures. when this bit is zero, it means that the structures have been completed. this bit can be used by software to manage mode switching, but it is not necessary for standard vga operation. refer to ?ga status register?on page 47. vga vertical sync select the vga_sync_sel ?ld of the grp_cfg4 register (bit 3, index 44h) selects the source of the vga vertical sync status (see table 22 on page 50). the internal vga sync status is used to set the vertical retrace interrupt (status is shown in bit 7 of the vga input status 0 register) and the vertical sync pulse (bit 3 of the vga input status 1 register.) vga read latches registers grp_rdlat3 (index 2bh) through grp_rdlat0 (index 28h) allow access to the 32 bit vga read latch. the vga read latch (de?ed by the vga criteria) is an entity which is loaded with a 32-bit frame buffer value for each vga memory read. read latch register [0] is the least signi?ant byte of the read latch. see ?ead latch registers?on page 46. vga dac mode bit 0 of the grp_vgacfg register enables the vga dac 8-bit mode (see ?ga con?uration register?on page 44). the default for the vga dac logic is the 6-bit mode. the 8-bit mode means that vga dac writes and reads to 3c9h are assumed to be 8-bit dac values, and are therefore transferred between the dac register block of the media buffer and the cpu bus unmodi?d. the 6-bit mode means that dac vga access to 3c9h are 6-bit dac values, and therefore a translation is done between the 6-bit value on the cpu bus and the 8-bit value in the dac register block of the media buffer. this is done for both reads and writes. vga i mplementation con?uration for vga btv2115 brook t ree 27 bt con?uration for vga the btv2115 requires the initialization of several registers and media buffer loca- tions for vga operation. the btv2115 provides drivers and bios routines to do this for common applications and environments. below is an outline of the re- quired steps. 1 decide how to allocate the media buffer. the vga frame buffer image will occupy the ?st 256kb of the media buffer. in the remainder, the programmer must allocate locations for two master structures, one graphics data structure, two timing structures, and one dac register structure. 2 set master pointer registers. write to the both master pointer a (pdc_msptra)and master pointer b (pdc_msptrb) registers so that they point to master structures a and b. 3 create master structure skeleton. initialize master structure a and b. the programmer must initialize the pkt_ordr, gd_pntr, ts_pntr, dr_pntr, dr_end, and clk_mod entries. the gd_y, gd_x, and ts_leng double words can be zeroed out if the vga structure generation bit is enabled (enable_vga_crtc_gen). other unused ?lds such as the video ?lds can also be zeroed out. table 5 provides recommendations for master structure ?lds. table 5. recommended master structure fields field comments pkt_ordr set the order to timing, graphics, dac register (io). thus pkt_ordr = eeeee526h. gd_pntr different gd structures can be allocated for each structure a and b, but it is unnecessary. ts_pntr the pointer in each structure must point to different locations; there must be two timing structures. dr_pntr the pointer in each structure must point to the same location. the vga module does not generate new dac register values when it requests a master pointer switch. it only generates new values when corresponding vga registers are modi?d. dr_end con?ure the dr_blk sub-?ld for no more than about 100 clk_mod a value of 0000b00bh works well for standard vga modes, assuming a serial clock of 35mhz. some super vga modes might need different values. vga i mplementation con?uration for vga btv2115 brook t ree 28 bt the vga was designed for a packet order of timing, graphics, and dac reg- ister (pkt_ordr = eeeee526h). a clk_mod value of 0000c00ch has worked well for standard vga modes. 4 create dac register structure skeleton. the code must build a dac register structure around the areas which will be written to by the vga module. below, table 6 provides a typical strategy for creating a dac structure. 5 write pixel clock pll registers. (for de?ition of the pll format, see btv2487 pacdac speci?ation .) if the mode is not a standard vga mode (i.e. a supervga mode), write the pll value to the location in the dac register structure which contains the pixel clock pll value. 6 write pdac pointer register. this register should be set to point within the dac register structure. typically, it will point to the second double word within the structure. 7 enable vga and vga structure generation. set the enable_vga_crtc and the enable_vga_crtc_gen bits. however, if the mode uses software generated timing structures, set the enable_vga_crtc_gen bit to zero. table 6. typical dac structure offset from dr_pntr (dwords) contents 0 write an entry which loads pacdac device address register to 100h. this is the address of the palette. 1 - 256 pdac_ptr points here. this is where the vga stores the palette. 257 write an entry which loads pacdac device address register to 0h. this is the address of the border color index. the vga module does not write to this address. 258 the vga module writes the border color index value here. 259 the vga module writes the pixel pll value here. 260 write the serial clock pll value here. the vga design is some- what ?xible, but 25 mhz works well for standard vga modes. 261 - (n-1) write pacdac register values for pacdac device addresses 03h through ffh. stop at ffh or when there are no more de?ed reg- isters. most register values in this range do not affect vga func- tionality and can be set to zero. n write an entry which loads pacdac device address register to 200h. n - end write pacdac register values for any remaining addresses above 200h. vga i mplementation support for vesa bios extension modes btv2115 brook t ree 29 bt support for vesa bios extension modes the vesa bios extension speci?ation de?es standard bios function calls which provide software access to resolutions, color depths, and frame buffer orga- nizations beyond the vga hardware standard. this allows software developers to take advantage of many unique implementations of super vga (svga) function- ality. vbe modes the btv2115 hardware supports vesa bios extension (vbe) functions and most modes. the vesa modes that use vga-compatible memory models support the use of vga hardware. those that use 256-color non-chain4 and direct color memory models are supported, but without vga hardware. in these modes the btv2115 behaves as a dumb frame buffer controller supporting 8-bit color depths. vga io operations will effect neither the frame buffer accesses nor the display format. status and control functions should be done through calls to the vbe func- tions. frame buffer models the vbe speci?ation de?es two ways to implement a frame buffer aperture: vga window or linear/?t model. the set mode function includes an extra bit which speci?s which model to use. the btv2115 supports both. for the vga windowing frame buffer model, the btv2115 provides dual real mode apertures via vga address space. each port may be con?ured for a 32k or 64k window size. the 32k and 64k mode aperture addresses are de?ed in table 75 on page 124. each port includes read/write capability and a paging mech- anism which allows an application to ?indow?into the frame buffer. for the linear/?t buffer model, the btv2115 chip provides a protected mode aperture which can be located anywhere within the cpu s 32-bit address space. for more information, refer to ?eal mode aperture?on page 127. timing structures and high resolution modes the vga timing structure generation mechanism is used to support applications which change modes by writing directly to vga crt controller registers, rather than making a bios call. however, a few issues arise with this mechanism in high- er resolutions modes such that applications have to use bios for non-standard vga modes. there is no standard mechanism for switching to high resolution modes independently of making a bios call. therefore, it is wiser for bios or ap- plication drivers to load the timing structure into the media buffer rather than rely upon the vga hardware to do it. this also means that the vga structure genera- tion mechanism must be disabled by clearing the enable_vga_crt_gen bit (bit 7) in the grp_cfg5 register. vga i mplementation support for vesa bios extension modes btv2115 brook t ree 30 bt the biggest issue that arises with vga hardware generated timing structures is the ?ed position of the lsync pulse, which works for standard vga resolutions but could fail for some svga resolutions. mode setting procedure the steps required to initialize a vbe mode depend on a couple of factors: does the mode use a vga compatible memory model? if not, the vga hardware must be disabled through the enable_vga_crt bit. can the mode use vga-generated timing structures? if not, the enable_vga_crt_gen should be set to ? to disable timing data generation. bios must load the timing structure. in general, here is the procedure: 1 initialize pacdac controller structures in the media buffer, if not already initialized. initialize the register ?lds which con?ure the vga module. 2 if the mode does not use a vga-compatible memory model (vbe mod- els 0 through 4), then disable vga crt controller functionality by clearing the enable_vga_crt bit (bit 2 of grp_cfg4). in this case, enable the real-mode or protected-mode aperture. 3 if the resolution exceeds standard vga modes (such as 720 x 400 or 640 x 480), disable generation of the timing structure. load the mode s tim- ing structure into the media buffer. 4 modify the clock modulation ?ld (clk_mod) of the master structure. like the timing structure, the clock modulation rate must be tailored for each mode. (see the ?acdac controller?chapter starting on page 195.) 5 modify the pixel clock ?lds and serial clock ?lds of the dac regis- ter structure. if the 25 mhz or 28 mhz pixel clock will be selected through the vga miscellaneous output register, then the pixel clock ?ld does not need to be modi?d. the vga will generate the pixel clock pll value automatically. 6 follow appropriate mode switching procedure. (see the ?acdac con- troller?chapter starting on page 195.) logical window control the vbe functions include logical window setup and control (such as setting the logical line width and adjusting the display start address). these functions can be used for horizontal panning, vertical scrolling, and display buffer switching for an- imation. the btv2115 chip provides the capability to support these functions in hard- ware, although horizontal panning must be used with caution. the display start ad- dress can be changed by modifying the gd_pntr ?ld of the master structure. the logical scan line length can be adjusted by modifying the ptch ?ld of the gd_x entry in the master structure. (see the ?acdac controller?chapter start- ing on page 195.) vga i mplementation support for vesa bios extension modes btv2115 brook t ree 31 bt when implementing horizontal panning, keep in mind the following. first, the start address has a resolution of 32 bits. thus in an 8-bit mode, the screen can be panned in only four-pixel increments. (bios can theoretically get around this lim- itation by modifying the timing structure to pan on a pixel basis.) second, when the start address is not aligned to 256-byte boundaries, the performance of the serial packet bus will be affected. each scan line could require more read transfer op- erations to the vram. in some modes, this slowdown will cause system failure. as a result, horizontal panning should only be supported if the resolution is feasi- ble and if the mode can support the performance degradation on the serial port. dac palette format the vbe includes a function to set/get the number of bits per palette primary col- or. for palette access via the vga 3c9h port, the btv2115 controller supports both 6-bit and 8-bit formats, which are the most common formats. the selection is made through bit 0 of the grp_vgacfg register. a ? indicates an 8-bit mode, while a ? indicates a 6-bit mode (refer to ?ga con?uration register?on page 44). this bit only affects accesses via the vga 3c9h port. palette operations via this address can be translated between 6-bit and 8-bit formats. when con?ured for 6- bit modes, palette operations via 3c9h are translated between 6-bit and 8-bit for- mats. on the other hand, any palette values stored directly into the frame buffer are always in the 8-bit format. however, bios can still perform the translation if the palette is accessed through the load/unload palette data function call. brook t ree 33 bt r egister d efinitions introduction the btv2115 presents both an i/o space interface and a memory interface to its in- ternal registers. in addition, pci bus implementations of the btv2115 present a pci con?uration space interface to certain registers (see ?ci con?uration space?on page 219). not all registers are accessible from i/o space nor are all reg- isters accessible from memory space. i/o space registers include the i/o addresses used by vga controllers as well as the i/o space registers used by dos-based game audio. some registers such as the gui accelerator registers and the win- dows-based audio/video registers are only available through cpu memory instruc- tions. some registers, such as bits 31:25 of the gui_ base register are accessible through i/o space and through the pci bus con?uration space. table 7 shows a complete list of the i/o port addresses that are implemented within the btv2115 and their corresponding alternate decode addresses (see ?ar- allel decoder interface?on page 266). notice that all i/o port addresses are present for software compatibility with either vga or dos based game audio, i.e. the btv legacy audio emulation. since these i/o spaces were required for soft- ware compatibility, they were extended to control most new btv2115 functions. in a pci environment, access to these exact i/o addresses are requested by de?ing two con?uration function spaces and declaring a vga compatible class code and a legacy sound device class code. for information on the pci interface refer to ?ci bus interface?on page 216. r egister d efinitions introduction btv2115 brook t ree 34 bt table 7. btv2115 i/o address map (1 of 3) i/o port alternate decoder port write read 0102 0102 mca pos 102 mca pos 102 03b4 33c4 vga crt index (mono) crt index (mono) 03b5 33c5 vga crt data (mono) crt data (mono) 03ba 33ca vga feature control (mono) input status reg 1 (mono) 03c0 23c0 vga attribute index/data attribute index 03c1 23c1 cycle accepted from bus but no operation performed. attribute data 03c2 23c2 vga miscellaneous output input status reg 0 03c3 23c3 mother board sleep mother board sleep 03c4 23c4 vga sequencer index vga sequencer index 03c5 23c5 vga sequencer data vga sequencer data 03c6 23c6 vga dac pixel mask vga dac pixel mask 03c7 23c7 vga dac address read mode vga dac state 03c8 23c8 vga pixel address write mode vga pixel address write mode 03c9 23c9 vga pixel data vga pixel data 03ca 23ca cycle accepted from bus but no operation performed vga feature control read 03cc 23cc cycle accepted from bus but no operation performed vga miscellaneous output read 03ce 23ce vga graphics controller index vga graphics controller index 03cf 23cf vga graphics controller data vga graphics controller data 03d4 23d4 vga crt index (color) vga crt index (color) 03d5 23d5 vga crt data (color) vga crt data (color) 03da 23da vga feature control (color) vga input status reg 1 (color) 46e8 46e8 adapter sleep adapter sleep 0220 0220 bank0 address bank0 status 0221 0221 bank0 data reserved 0222 0222 bank1 address bank1 status 0223 0223 bank1 data reserved 0224 0224 mixer address reserved 0225 0225 mixer data mixer data 0226 0226 dsp reset reserved r egister d efinitions introduction btv2115 brook t ree 35 bt 0227 0227 reserved reserved 0228 0228 bank address bank status 0229 0229 bank data bank data 022a 022a reserved dsp read data 022b 022b reserved reserved 022c 022c dsp cmd-data dsp write status 022d 022d reserved reserved 022e 022e reserved dsp read data status 022f 022f reserved reserved 0240 0240 bank0 address bank0 left status 0241 0241 bank0 data reserved 0242 0242 bank1 address bank1 status 0243 0243 bank1 data reserved 0244 0244 mixer address reserved 0245 0245 mixer data mixer data 0246 0246 dsp reset reserved 0247 0247 reserved reserved 0248 0248 bank address bank status 0249 0249 bank data bank data 024a 024a reserved dsp read data 024b 024b reserved reserved 024c 024c dsp cmd-data dsp write status 024d 024d reserved reserved 024e 024e reserved dsp read data status 024f 024f reserved reserved 0388 0388 bank0 address bank0 status 0389 0389 bank0 data reserved 038a 038a bank1 address bank1 status 038b 038b bank1 data reserved table 7. btv2115 i/o address map (2 of 3) i/o port alternate decoder port write read r egister d efinitions introduction btv2115 brook t ree 36 bt the vga emulation supports six distinct sets of i/o space addresses: vga graphics registers, vga sequencer registers, vga crtc registers, vga at- tribute registers, vga color registers, and vga external registers. the graphics registers are accessed by loading the index of the desired register into the graphics index register at i/o port address 3ceh followed by reading or writing the desired data from the register through the graphics data register at i/ o port address 3cfh. see ?ga graphics registers (i/o mapped) on page 38 for more detail. similarly, vga sequencer registers are accessed by loading the index of the de- sired register into the sequencer index register at i/o port address 3c4h followed by reading or writing the desired data from the register through the sequencer data register at i/o port address 3c5h. see ?ga sequencer registers (i/o mapped) on page 62 for more detail. the vga crt controller registers are accessed by a similar mechanism with the crtc index registers at either i/o port address 3b4h or 3d4h and the crtc data register at either i/o port address 3b5h or 3d5h. see ?ga crt controller (i/o mapped) on page 69 for more detail. the vga attribute registers are also indexed, but the mechanism has the stan- dard vga characteristic that both the index and data values pass through the same i/o port address at 3c0h. reading 3c0h returns the contents of the indexed at- tribute register. reading 3c1h returns the contents of the attribute index register. see ?ga attribute controller (i/o mapped) on page 79 for more detail. the vga external registers are accessed at their speci?d i/o port addresses without further indexing. see ?ga general / external registers (i/o mapped) on page 84 for more detail. the vga color registers have their own, standard index mechanism involving i/o port addresses 3c6h, 3c7h, 3c8h, and 3c9h. see ?ga color registers (i/o mapped) on page 89 for more detail. 3f8-3ff 3f8-3ff comm port 0 comm port 0 2f8-2ff 2f8-2ff comm port 1 comm port 1 3e8-3ef 3e8-3ef comm port 2 comm port 2 2e8-2ef 2e8-2ef comm port 3 comm port 3 0201 0201 joy stick/game port joy stick/game port 0330-0331 0330-0331 mpu port mpu port table 7. btv2115 i/o address map (3 of 3) i/o port alternate decoder port write read r egister d efinitions introduction btv2115 brook t ree 37 bt the btv2115 legacy audio emulation supports three sets of i/o space address- es. 388h through 38bh provide access to the yamaha opl3 registers. the bank of i/o port addresses from 220h to 24fh is duplicated in the bank of i/o port address- es from 240h to 22fh. only one of these banks can be active at a time. only one dos-based game audio subsystem can be active at a time so that if another is in- stalled, the btv2115 legacy audio emulation should be disabled, see ?egacy audio fm registers (i/o mapped) on page 91, ?udio registers (memory mapped) on page 96, and ?udio interface?chapter starting on page 271. r egister d efinitions vga graphics registers (i/o mapped) btv2115 brook t ree 38 bt vga graphics registers (i/o mapped) the btv2115 mediastream controller uses indexed addressing to access the 149 control registers in this block. the ?st nine registers are standard vga registers and the remainder are btv2115 extensions. the offset into the vga data space is provided through 3cfh. graphics index port name: grp_index port: 3ceh, read/write size: 8 bit function: the value in this register determines which register in the graphics controller block is written or read when performing an i/o cycle to the grp_data address. only the lower 4 bits of the index register are valid when the btv2115 extensions are locked. when the btv2115 ex- tensions are unlocked, all 8 bits of the index register are used. bit 7:4 are held at zero, when locked. graphics data port name: grp_data port: 3cfh, read/write size: 8 bit function: the various vga graphics registers are accessed through this i/o whenever their corresponding index has been loaded into grp_index. set/reset register name: grp_sr index: 3cfh.00h, read/write size: 8 bit function: this register is loaded with the pattern to be written to the display planes in write mode 0 or write mode 3. there is a 1 to 1 correspon- dence between the bits in this register and the display planes. the bit contents of the set/reset register are shown in table 8. table 8. set/reset register bit function 7:4 reserved 3 set/reset plane 3 2 set/reset plane 2 1 set/reset plane 1 0 set/reset plane 0 r egister d efinitions vga graphics registers (i/o mapped) btv2115 brook t ree 39 bt enable set/reset register name: grp_esr index: 3cfh.01h, read/write size: 8 bit function: this register enables or disables the individual planes affected by the set/reset register. this register is only used in write mode 0. the bit contents of the enable set/reset register are shown in table 9. color compare register name: grp_cc index: 3cfh.02h, read/write size: 8 bit function: the color compare bits contain the value to which all eight bits of the corresponding memory plane are compared. the color don t care reg- ister establishes the mask for the memory planes. this register is only used in read mode 1. a ? is returned for the plane positions where the bits of all 4 planes equal the color compare register. the bit con- tents of the color compare register are shown in table 10. table 9. enable set/reset register bit function 7:4 reserved - hardwired to 0h 3 enable set/reset plane 3 2 enable set/reset plane 2 1 enable set/reset plane 1 0 enable set/reset plane 0 table 10. color compare register bit function 7:4 reserved - hardwired to 0h 3 color compare plane 3 2 color compare plane 2 1 color compare plane 1 0 color compare plane 0 r egister d efinitions vga graphics registers (i/o mapped) btv2115 brook t ree 40 bt data rotate register name: grp_rot index: 3cfh.03h, read/write size: 8 bit function: this register contains the rotate count and the function select ?lds. the rotate count ?ld speci?s the number of bit positions to rotate data right by the cpu in write mode 0 or 3. the function select ?ld selects a boolean between the write data and the data contained in the read latches. the logical functions are enabled for write mode 0, 2, and 3. the bit contents of the data rotate register are shown in table 11. read map select register name: grp_rdpln index: 3cfh.04h, read/write size: 8 bit function: this register selects which planes are read in read mode 0. the bit contents of the read map select register are shown in table 12. table 11. data rotate register bit function detail 7:5 reserved hardwired to b?00 4:3 function select 1:0 00 = data unmodi?d 01 = data anded with data in latches 10 = data ored with data in latches 11 = data xored with data in latches 2:0 rotate count 2:0 amount to rotate right cpu data table 12. read map select register bit function detail 7:2 reserved hardwired to 00h 1:0 map select 1:0 00 = plane 0 01 = plane 1 10 = plane 2 11 = plane 3 r egister d efinitions vga graphics registers (i/o mapped) btv2115 brook t ree 41 bt mode register name: grp_mode index: 3cfh.05h, read/write size: 8 bit function: this register controls the vga read and write modes, data shift reg- isters, and other addressing modes. the bit contents of the mode reg- ister are shown in table 13. table 13. mode register bit function detail 7 reserved hardwired to 0 6 256 color mode 0 = con?ure shift registers for 2, 4, or 16 colors 1 = con?ure shift registers for 256 colors 5 shift register 0 = con?ure shift registers for ega/vga compatibility 1 = con?ure shift registers for cga compatibility 4 odd/even 0 = normal frame buffer read addressing 1 = even/odd addressing - use cpu address bit 0 to select odd or even planes on reads 3 read mode 0 = read mode 0 - read data from planes selected by read map select register (has no effect if bit 3 of the sequencer memory mode register = 1) 1 = read mode 1 - read comparison of the planes and color compare register 2 reserved hardwired to 0 1:0 write mode 1:0 the write mode ?ld controls the con?uration of the datapath for vga writes. it controls how the set/ reset, enable set/rest, logic unit, data rotator, and bit mask logic are interconnected. consult a referenced vga publication for more detailed information. 00 = write mode 0 01 = write mode 1 10 = write mode 2 11 = write mode 3. r egister d efinitions vga graphics registers (i/o mapped) btv2115 brook t ree 42 bt graphics miscellaneous register name: grp_misc index: 3cfh.06h, read/write size: 8 bit function: this register controls the vga display mode, monochrome graphics emulation, and odd/even addressing. the bit contents for this register are shown in table 14. color don? care register name: grp_ccx index: 3cfh.07h, read/write size: 8 bit function: this register selects which planes will be used in a color comparison between the values in the graphics controller color compare register and the data read from video memory. this comparison is only done while in read mode 1.if the map bit = 1, color comparison is enabled for that plane or map. the bit contents of the color don t care register are shown in table 15. table 14. graphics controller: miscellaneous register bit function detail 7:4 reserved hardwired to 0h 3:2 memory map 1:0 00 = 128kb a0000-bffffh 01 = 64kb a0000-affffh 10 = 32kb b0000-b7fffh 11 = 32kb b8000-bffffh 1 chain odd/even this bit controls whether cpu address a0 is used for memory address bit 0, or replaced with another value (chain- ing). consult a vga text for more detail. 0 = normal addressing 1 = chain odd/even function is enabled 0 graphics mode 0 = text mode 1 = graphics mode table 15. color don? care register bit function 7:4 reserved - hardwired to 0h 3 memory map 3 2 memory map 2 1 memory map 1 0 memory map 0 r egister d efinitions vga graphics registers (i/o mapped) btv2115 brook t ree 43 bt bit mask register name: grp_bitmask index: 3cfh.08h, read/write size: 8 bit function: this register is a mask for modifying displayed pixels. a bit set to a 1 allows the corresponding pixel to be changed. the lsb corresponds to the rightmost pixel in the group. this register is disabled with write mode 1. the bit contents of the bit mask register are shown in table 16. table 16. bit mask register bit function 7:0 bit mask r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 44 bt extension registers accessed via vga space (i/o mapped) this section describes general purpose i/o registers accessed through the vga space. the offset into the vga data space is through 3cfh. vga con?uration register name: grp_vgacfg index: 3cfh.16h, read/write size: 8 bit function: writing 01h to this register enables the vga dac 8-bit mode. the de- fault for the vga dac logic is the 6-bit mode. the 8-bit mode means that vga dac writes and reads to 3c9h are assumed to be 8-bit dac values, and are therefore transferred between the dac register block of the media buffer and the cpu bus unmodi?d. the 6-bit mode means that dac vga access to 3c9h are 6-bit dac values, and there- fore a translation is done between the 6-bit value on the cpu bus and the 8-bit value in the dac register block of the media buffer. this is done for both reads and writes. chip id registers name: grp_cid[1:0] index: 3cfh.18h:17h, read only size: 16 bit function: these registers contain the 16 bit btv2115 chip id value. if the chip design were released in june 1995, the chip id would be 9506h. rom page register name: grp_rompage index: 3cfh.19h, read/write size: 8 bit function: for vl mode, the 5 least signi?ant bits of this register are appended to the vga_rom aperture cpu address to select any 32kb page in the 1mb flash rom. for pci mode, this register has no effect since cpu address bits [19:2] are passed to the rom (refer to ?ga rom aperture?on page 129). pll25 select registers name: grp_25pll[2:0] index: 3cfh.1ch:1ah, read/write size: 24 bit function: when the vga miscellaneous output register is programmed to se- lect a 25mhz pixel clock for the vga, this register contains the pll register value that is programmed into the pacdac chip. the vga crtc block writes this value into the dac register block of the media r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 45 bt buffer so that it will be sent to the pacdac on the packet interface. the bit contents for this register are shown in table 17. for information on the pixel clock, refer to the btv2487 pacdac speci?ation , ?ixel clock pll?section. pll28 select registers name: grp_28pll[2:0] index: 3cfh.1fh:1dh, read/write size: 24 bit function: when the vga miscellaneous output register is programmed to se- lect a 28mhz pixel clock for the vga, this register contains the pll register value that is programmed into the pacdac chip. the vga crtc block writes this value into the dac register block of the media buffer so that it will be sent to the pacdac on the packet interface. the bit contents for this register are shown in table 17. for information on the pixel clock, refer to the btv2487 pacdac speci?ation , ?ixel clock pll?section. gui base registers name: grp_gui_base[3:0] index: 3cfh.23h:20h, read/write size: 32 bit function: these registers select the base addresses for the four 8mb windows of the graphics users interface/media buffer aperture. for detail on the usage and bit de?itions of these registers refer to ?ui base address register?on page 123 of the ?pu address space apertures?chapter. table 17. pll 25mhz and 28mhz select registers bits function 23:16 reserved 15 source crystal reference selection 0= xtal25 (24.576 mhz) 1= xtal17 (16.934 mhz) 14:12 . reserved 11:10 post scalar factor (variable l) 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8 9:6 value of n, range: 1 to 15 (0h to fh) 5:0 value of m, range: 1 to 63 (0h to 3fh) the pixel rate is de?ed as: (m/(nxl)) x crystal frequency r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 46 bt dac alias pointer registers name: grp_pdac[1:0] index: 3cfh.27h:26h, read/write size: 16 bit function: when the vga module needs to update values in the dac register block of the media buffer, this register determines the base address of the region where it will make its modi?ations. if we call the media buffer pointer pdac_ptr, it is generated as follows: pdac_ptr[21:19] = grp_pdac1[2:0] pdac_ptr[18:11] = grp_pdac0[7:0] pdac_ptr [10:0] = 0 the bit contents for the grp_pdac register are shown in . the vga block is responsible for updating the dac palette, the border color index value, and the pixel clock pll based on values written to vga i/o registers. therefore writes to the media buffer are triggered by writes to dac_data (?ac data register?on page 90), misc_out_w (?rite miscellaneous out- put register?on page 87), and att_ovrs (?verscan color register?on page 81). data retrieval reads from the media buffer are triggered by reads from the dac_data register only. the vga block always puts the dac palette at locations pdac_ptr + 0 through pdac_ptr + 1023. (the rgb values for color index 0 go at pdac_ptr + 0 to pdac_ptr + 2. color index 1 values go from pdac_ptr + 4 to pdac_ptr + 6, and so on.) it puts the border index value at pdac_ptr + 1028, and the pixel clock pll value at pdac_ptr + 1032. refer to ?ac data?on page 206 for additional information on the dac. read latch registers name: grp_rdlat[3:0] index: 3cfh.2bh:28h, read only size: 32 bit function: these four registers allow access to the 32 bit vga read latch. the vga read latch is an entity de?ed by vga criteria which is loaded with a 32-bit frame buffer value for each vga memory read. read latch register [0] is the least signi?ant byte of the read latch. table 18. grp_pdac registers register bits description grp_pdac1 7:3 reserved - all zeroes 2:0 three bits of the 22 bit media buffer pointer - pdac_ptr[21:19] grp_pdac0 7:0 eight bits of the 22 bit media buffer pointer - pdac_ptr[18:11] r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 47 bt vga status register name: grp_vgastat index: 3cfh.2ch, read/write size: 8 bit function: this register returns a ? in bit position zero if pointing to the attribute data register and a ? if pointing to the attribute index register, re- ?cting the direction of a write to 3c0h as either the attribute index or attribute data register. this register also reports the status of the vga crt controller. bit 1of this register re?cts crt generator status. when bit 1 = 1, the crt controller is busy generating the crtc data structures. when bit 1 = 0, the crt controller is ?ished generating data structures. con?uration registers name: grp_cfg[7:0] index: 3cfh.47h:40h, read/write size: 64 bit function: these eight registers allow operating parameters to be set at power-on for the btv2115 and modi?d later for desired chip operation through video bios. for more information see the ?on?uration registers starting on page 133. table 19 through table 26 de?e the contents of the con?uration registers. table 19. con?uration register <7> (grp_cfg7) bits function 7 pci_pref_base (vram data bus 25) - for pci bus only. 1 = enable pci prefetch base register. must also be enabled by the pci con?uration mechanism. allows the 32mb aperture to also appear as a prefetchable address range. refer to ?ci prefetch- able base address registers?on page 222 0 = hide 32mb prefetchable base address 6 wake up state at power on (vram data bus 24) 1 = vga awake at power on 0 = vga asleep at power on 5:0 vram type: read only ?ld, indicates the type of vram attached to the btv2115. contains the resistor strapped state of vram data bus [15:10]. see "supported vram types," table 139 on page 229. r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 48 bt table 20. con?uration register <6> (grp_cfg6) bits function 7 1 = pci two clock write enable. the cycle must be a memory write cycle and the address must match the non-zero value in grp_gui_base[31:25] (see ?ui base registers?on page 45). (default) 0 = pci two clock write not enabled. 6 1 = burst memory write enable (default) 0 = for all cycle types, attempts to burst are disconnected with a type c disconnect/retry mechanism (see the pci local bus speci?ation, revision 2) pci_st op is asserted with p ci_trdy deasserted (see ?ci bus interface?on page 216). the btv2115 takes the ?st data phase and disconnects the second. 5 reserved 4 interrupt request polarity 1 = irq active high (default) 0 = irq active low 3 audio insert ?ter clock select: selects the ?ter clock rate in use for the switched cap ?ter. this bit is only read by software and is set by vram data bus 23. 1= 100x external ?ter 0 = 50x external ?ter 2 enable save/restore location in seq_unlock register (see ?nlock register?on page 67) 1 = enable context save/restore 0 = disable (default) 1 memory burst size max 4 for gui and video bursts 1 = max of 4 0 = max of 8 (default) 0 block write enable for gui / gui bist control 1 = gui will use block write where appropriate (default) 0 = gui will use byte enable controlled writes even for cases where block write would offer signi?ant performance improvement. - or- 0 = run gui bist if set to zero when grp_cfg4[0] (gui enable) transitions to high (is set to 1), the gui ram built-in test (bist) will run on the gui result fifo rams. bit 19 of the guireg_depth register will re?ct gui_busy status while bist is running. bist pass/fail and comple- tion status is re?cted in the guireg_cfg register (see table 107 on page 177). to disable block writes without running bist, set grp_cfg4[0] = 1 before writing block write enable to zero. r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 49 bt table 21. con?uration register <5> (grp_cfg5) bits function 7 enable vga crtc generator (enable_vga_crt_gen) 1 = crtc structure generation is enabled so that certain vga i/o cycles will modify pacdac control structures in the vram. this includes master structure and the timing structure. this bit must be set in conjunction with grp_cfg4[2], the enable vga crtc bit. this bit does not affect the generation of graphics data nor dac register data. 0 = no vram cycles issued in response to vga i/o cycles (default). 6 clock modulator reset: 1 = force pixel tag rst to the btv2487 from the pacdac controller until cleared 0 = normal operation (default) 5:0 monitor id bits: allow monitors to be identi?d by reading their unique id. these bits are loaded at the end of reset from a ?44 which buffers the monitor id pins from the vga connector to the vram data bus. bits [5:4] are used as board revision information for bios and drivers. the bios init sequence (see table 23) saves these bits to the bios save area (top 128 bytes of vram) and overwrites bits [1:0] with the vram size as follows: bits[1:0] -- 00 = 1m 01 = 2m 10 = 3m 11 = 4m r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 50 bt table 22. con?uration register <4> (grp_cfg4) (1 of 2) bits function 7 dac snoop: allows the cpu bus to contain an additional write-only pal- ette dac which share address space with the btv2115 vga color regis- ters. this includes 03c6-03c9h. the btv2115 will capture vga color register writes, but will not drive any cpu bus handshaking signals. this is called snooping the writes. reads are handled normally. 1 = vga dac writes are snooped, while vga dac reads sourced from the btv2115 as normal. 0 = both reads and writes are handled by btv2115(default). 6 rom write enable 1 = enable flash rom write mode 0 = disable flash rom write cycles (default) 5 bios rom enable for vga rom aperture at 000c000h -000c7fffh. 1 = enable rom access 0 = disable rom aperture. rom cycles on cpu bus are ignored. 4 this bit is valid for vl bus only. rom hole from 000c6000h-000c67ffh used to be a compatibility prob- lem for some network cards. 1 = enable rom hole in memory address map, i.e. the btv2115 will not respond to rom reads within the rom hole. 0 = btv2115 responds to rom reads within the rom hole, if bios rom is enabled by bit 5. r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 51 bt 3 vga_sync_sel - select the source of the vga vertical sync status. the internal vga sync status is used to set the vertical retrace interrupt (sta- tus is shown in bit 7 of the vga input status 0 register) and the vertical sync pulse (bit 3 of the vga input status 1 register.) 1 = pseudo vga sync. the sync status is asserted when the vga crtc ?ishes drawing to display buffer. 0 = real vga sync. vga vertical sync status is based on monitor vertical sync (default) 2 enable vga crtc block (enable_vga_crtc). the vga crtc block maps the vga frame buffer into the display buffer, according to the current vga register settings. this bit must be set to enable generation of graph- ics data, parts of the master structure, and the timing structure. however, if the enable_vga_crtc_gen bit (grp_cfg5, bit 7) is not set, then the vga will only be able to generate the graphics data. 1 = enable the vga crt controller. 0 = disable the vga crt controller, force crtc into idle state (default). 1 enable pacdac controller to send timing, cursor, video and graphics packets to the btv2487. 1 = pacdac controller enabled 0 = no monitor refresh functions (default). 0 gui enable 1 = enable gui and gui portions of fba logic 0 = reset all of gui plus gui portions of fba logic (default) ?ui portions?are de?ed as: anything having to do with the function or access of the gui vram queue. anything having to do with reading or writing queued or non-queued registers, including registers that control bit ?pping in the flippin map. table 22. con?uration register <4> (grp_cfg4) (2 of 2) bits function r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 52 bt table 23. con?uration register <3> (grp_cfg3) bits function 7 bios_reset_state indicates bios init sequence has been exe- cuted one or more times. 0 = bios init sequence not executed (default) 1 = bios init sequence has been executed 6 decode test: enable alternate decode address space so that the vga real mode aperture a0000-bffff becomes 860a0000- 860bffffh, the vga rom aperture at c0000-c7fff becomes 860c0000h-860c7fffh. the vga i/o s at 03cxh become 23cxh. both mono and color vga registers at 03bxh and 03dxh become 33cxh. audio i/o registers remain unchanged as does the 46e8h adapter sleep address. 1 = enable alternate decodes. 0 = enable normal decodes. 5 sleep bit: the btv2115 can be con?ured as a vga motherboard device which responds to sleep address 03c3h or as an adapter card vga which responds to sleep address 046e8h and the mca position address at 0102h. 1 = adapter sleep at 46e8h and 0102h 0 = motherboard sleep at 03c3h 4:3 these read only bits indicate which cpu bus type is in use by the btv2115. the btv2115/v version can initialize to any valid combina- tion of bits, while the btv2115/p can only initialize to 0. 00 = vl bus 01 = pci bus 2 fast gui: this read-only bit indicates whether the vram gui queue is present in the btv2115 1 = fast 0 = slow 1 reserved read-only. always = 1 0 reserved read-only. always = 1 r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 53 bt table 24. con?uration register <2> (grp_cfg2) bits function 7:0 refresh rate count. this value is used as a down count to determine when to issue refresh cycles to vram. units are mclk/8. time between successive refresh cycles is ((period mclk 8) grp_cfg2). one row in each four vram bank is refreshed per refresh cycle. initial value is set to 0xb4. table 25. con?uration register <1> (grp_cfg1) bits function 7 reserved - write 0 6 block mode. 0 = 4x8 block write mode (default) 1 = ti 4mbit block write mode or 2mbit block write mode (4x4)x4 5 rom speed: this bit selects the speed of the rom interfaced to the btv2115. 0 = 120ns 1 = 70ns 4 sam length: this bit sets the length of the serial shift register in vram. 0 = 256 entries (default) 1 = 512 entries 3 communications decode enable: enables pci/vl decoder to capture communications port addresses and pass the i/o cycles to the vram data bus as rom cycles above 512k of flash rom space. 1= accept one of four comm port i/o register bank decodes 0= ignore communications port i/o 2:1 communications port bank select when bit 3 =1 00= comm port 0 @ 03f8-03ff maps to 07803f8-f 01= comm port 1 @ 02f8-02ff maps to 07802f8-f 10= comm port 2 @ 03e8-03ef maps to 07803e8-f 11= comm port 3 @ 02e8-02ef maps to 07802e8-f 0 midi port decode enable: enables pci/vl decoder to capture mpu401 i/o cycles and map them to the flash rom space. 1 = accept i/os to 0330-0331 and map to 07a0330-1 0= ignore mpu 401 i/o cycles r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 54 bt i 2 c control register name: grp_i2c_ctrl index: 3cfh.4bh, read/write size: 8 bit function: the i 2 c serial control interface speci?s the use of either the master or slave a bus or b bus. for more information on this register, refer to ? 2 c control write register?on page 138. i 2 c slave control register name: grp_i2c_sctrlr, grp_i2c_sctrlw index: 3cfh.4ch, read/write size: 8 bit function: this register is the slave device i 2 c control bits. the slave control reg- isters are de?ed differently for read and write operations. for bit def- initions of these registers, refer to ?2c slave control read register on page 152. table 26. con?uration register <0> (grp_cfg0) bits function 7 joy stick decode enable: enables pci/vl decoder to capture game port i/o cycles and map them to the flash rom space. 1 = accept i/os to 0201 and map to 07c0201 0 = ignore game port i/o cycles 6:5 ram speed: this ?ld sets the access rate of the vram. 00 = 80 ns (default) 01 = 70 ns 10 = 60 ns 11 = default 80 ns, writes 00 4 dual cas: this bit determines whether a vram requires dual cas support. con?ure btv2115 for dual cas vrams. 1 = dual cas 0 = dual we 3 reserved for spare b 2 disable refresh: 1 = disable vram refresh cycles 1 reserved for spare a 0 2 mbit refresh. 0 = force dsf low during cbrr cycles 1 = force dsf high during cbrr cycles dsf is device special function select. cbrr is cas before ras refresh with reset. r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 55 bt i 2 c slave data register name: grp_i2c_sdata index: 3cfh.4dh, read/write size: 8 bit function: this register contains the slave device i 2 c data. when this register is read it contains the contents of the slave module i 2 c input data buffer. system software should poll the done bit in the i 2 c slave control register to verify completion of a transaction before reading to avoid corruption of incoming data. when this register is written it contains data to be transmitted over the i 2 c interface. system software should poll the done bit in the i 2 c slave control register to verify completion of a transaction before writing to avoid corruption of outgoing data. for bit de?itions of this register, refer to ?2c slave data regis- ter?on page 151. i 2 c master control register name: grp_i2c_mctrlr, grp_i2c_mctrlw index: 3cfh.4eh, read/write size: 8 bit function: this register contains the master device i 2 c control bits. for bit de?i- tions of this register, refer to ? 2 c master control read register?on page 142 and ? 2 c master control write register?on page 144. i 2 c master data register name: grp_i2c_mdata index: 3cfh.4fh, read/write size: 8 bit function: this register contains the master device i 2 c data. when this register is read, it contains the contents of the master i 2 c input data buffer. sys- tem software should poll the done bit in the i 2 c master control reg- ister to verify completion of a transaction before reading to avoid corruption of incoming data. when this register is written it contains data to be transmitted over the i 2 c interface. system software should poll the done bit in the i 2 c master control register to verify completion of a transaction before writing to avoid corruption of outgoing data. for more bit contents information on this register, refer to ? 2 c master data register?on page 141. master structure a address register name: pdc_msptra[2:0] index: 3cfh.59h:57h, read/write size: 24 bit function: these three registers contain the dword address for the vram starting location of master structure a. the registers are concatenated to form the 20 bit pointer ?ld; refer to table 27. only one master structure (a or b) can be active at a time. r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 56 bt for more information, refer to ?aster structure?on page 197 of the ?ac- dac controller?chapter. master structure b address register name: pdc_msptrb[2:0] index: 3cfh.5ch:5ah, read/write size: 24 bit function: these three registers contain the dword address for the vram loca- tion of master structure b. the registers are concatenated to form the 20 bit pointer ?ld; refer to table 27. only one master structure (a or b) can be active at a time. for more information, refer to ?aster structure?on page 197 of the ?ac- dac controller?chapter. pacdac controller status register name: pdc_stat index: 3cfh.5dh, read only size: 8 bit function: this register monitors the pacdac controller status. the bit contents of the pacdac controller status register are shown in table 28. pdc_stat[0] reports which master structure (a or b) is in use; and pdc_cntl[0] is used to request a switch in master structure pointer. for exam- ple, a 1 in pdc_cntl[0] and a 0 in pdc_stat[0] indicates that a switch from a to b has been requested, but has not been executed. the pacdac controller up- dates the master structure pointers at the start of a frame, after all timing structure data for the frame is sent and all data for the last line is sent to the pacdac. dual pointers for each video window are supported to increase the quality of displayed video images. these pointers, dv1_pntra, dv1_pntrb, dv2_pntra, dv2_pntrb are loaded via the master structure initialization mechanism at the start of each frame. each pointer indicates the locations of buff- ered video data with two buffers allocated for each video window. switching from a to b and b to a is controlled by the video module which is outside the pac- dac controller module. the video module sets or clears ?gs for dv1 and dv2 to tell the pacdac controller which pointer (a or b) to use for the two video windows. the effects of these ?gs occurs at the start of each frame. table 27. master structures a and b address registers bits function 24:23 not used 22:02 dword address for the vram starting address 01:00 not used r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 57 bt pacdac controller control register name: pdc_cntl index: 3cfh.5eh, read/write size: 8 bit function: this register controls the pacdac controller functions for switching pdc_mspntr and halting the sequencer. the bit contents of the pacdac controller control register are shown in table 29. pdc_cntl[0] is used to request a switch in master structure pointer; and pdc_stat[0] reports which master structure (a or b) is in use. for example, a 1 in pdc_cntl[0] and a 0 in pdc_stat[0] indicates that a switch from master structure a to master structure b has been requested, but has not been executed. the pacdac controller updates the master structure pointers at the start of a frame, after all timing structure data for the frame is sent and all data for the last line is sent to the pacdac. table 28. pacdac controller status register bits function detail 7 reserved 6 vert_disp_en 0 = disabled 1 = enabled 5 lsync 0 = disabled 1 = enabled 4 dv2_pntr status 0 = dv2_pntra in use (default) 1 = dv2_pntrb in use 3 dv1_pntr status 0 = dv1_pntra in use (default) 1 = dv1_pntrb in use 2 reserved 1 frame sync status bit 0 = frame active 1 = starting new frame 0 mspntr status 0 = mspntra in use (default) 1 = mspntrb in use r egister d efinitions extension registers accessed via vga space (i/o mapped) btv2115 brook t ree 58 bt table 29. pacdac controller control register bits function detail 7:5 reserved 4 screen mode 1 = interlaced screen 0 = non-interlaced screen 3 reserved - write 0 2 eof halt mode end of frame disable. 0 = normal operation 1 = disable pacdac at end of current frame and clear grp_cfg4[1] (pacdac enable) 1 eol halt mode end of line disable. 0 = normal operation 1 = disable pacdac at end of current line and clear grp_cfg4[1] (pacdac enable) 0 mspntr usage com- mand bit 0 = use mspntra at next eof 1 = use mspntrb at next eof r egister d efinitions vga pci con?uration space (i/o mapped) btv2115 brook t ree 59 bt vga pci con?uration space (i/o mapped) the btv2115 graphics controller uses the following registers to access the pci con?uration space from the vga io space. for additional information, refer to ?ci con?uration space?on page 219. the offset into the vga data space is 3cfh. read pci prefetchable base address register name: grp_pbase index: 3cfh.24h, read only size: 8 bit function: this register provides read access to the pci prefetchable base address register. the bits are de?ed in table 30. read pci rom base address register name: grp_rombase index: 3cfh.25h, read only size: 8 bit function: this register provides read access to the pci rom base address regis- ter. the bits are de?ed in table 31. table 30. read pci prefetch base address bits description 7:1 pci_pref_base0[31:25] prefetch address, refer to ?ci prefetch- able base address registers?on page 222 0 always 0 table 31. read pci rom base address bits description 7:0 pci_rom_base0[31:24] rom address, refer to ?ci rom base address register?on page 223 r egister d efinitions vga pci con?uration space (i/o mapped) btv2115 brook t ree 60 bt read pci enable registers name: grp_pci_en index: 3cfh.2dh, read only size: 8 bit function: this register provides read access to various pci enable register val- ues. the bits are de?ed in table 32. table 32. read pci enable registers bits description 7:5 always 0 4 pci enable io cycles in the audio range. pci_io1_en value speci?d in pci_command1[0]; refer to ?ci command registers?on page 220 3 pci enable snoop on dac. pci_snoop_dac value speci?d in pci_command0[5]; refer to ?ci command registers?on page 220 2 pci enable memory cycles. pci_mem_en value speci?d in pci_command0[1]; refer to ?ci command registers?on page 220 1 pci enable io cycles in the vga address space. pci_io0_en value speci?d in pci_command0[0]; refer to ?ci command registers?on page 220 0 pci enable rom cycles. pci_rom_en value speci?d in pci_rom_base0[0]; refer to ?ci rom base address register?on page 223 r egister d efinitions sev registers (i/o mapped) btv2115 brook t ree 61 bt sev registers (i/o mapped) the sev player registers are de?ed in detail starting on page 185 of ?oftware encoded video (sev) player?chapter. below are brief summaries of the sev reg- isters. softvideo controller write register name: grp_sv_ctrlw[3:0] index: b4h:b1h, write only size: 32 bit function: refer to ?ev controller write register?on page 189. softvideo controller read register name: grp_sv_ctrlr[3:0] index: b4h:b1h, read only size: 32 bit function: refer to ?ev controller read register?on page 191. r egister d efinitions vga sequencer registers (i/o mapped) btv2115 brook t ree 62 bt vga sequencer registers (i/o mapped) the sequencer uses indexed addressing to access seven different control registers. the ?st six registers are standard vga registers. the seventh register is a btv2115 extension. the offset into the vga sequencer space is 3c5h. sequencer index register name: seq_index port: 3c4h, read/write size: 8 bit function: this register speci?s the register in the sequencer block to be accessed by the next i/o read or write to the seq_data address. only bits 2:0 are writable. bits 7:3 are hardwired to zero. sequencer data port name: seq_data port: 3c5h, read/write size: 8 bit function: this port accesses the sequencer data registers. the register accessed depends on the value of seq_index. reset register name: seq_rst index: 3c5h.00h, read/write size: 8 bit function: this register has no effect on the behavior of btv2115. a 00h should be written to this register during mode set; bits 7:2 are hardwired to ze- ro. clocking mode register name: seq_clk index: 3c5h.01h, read/write size: 8 bit function: this register contains the ?lds necessary to establish the video clock timing and control display refresh. the bit contents of the clocking mode register are shown in table 33. the options for the shift register control are shown in table 34. r egister d efinitions vga sequencer registers (i/o mapped) btv2115 brook t ree 63 bt map mask register name: seq_wpmask index: 3c5h.02h, read/write size: 8 bit function: this register masks write access to the video buffer planes by the host cpu. the bit contents of the map mask register are shown in table 35. table 33. clocking mode register bits function detail 7:6 reserved hardwired to 00 5 display refresh 0 = normal operation 1 = display refresh stops 4 shift & load 32 control display shift registers 3 dotclk 0 = normal operation 1 = divide by 2 2 shift and load 16 control display shift register 1 reserved hardwired to 0 0 8/9 dot clocks 0 = 9 dot wide character clock 1 = 8 dot wide character clock table 34. shift & load control bits bits 4 &2 function 00 every character clock 01 every 2nd character clock 10 every 4th character clock 11 every 4th character clock table 35. map mask register (1 of 2) bit function detail 7:4 reserved hardwired to 0h r egister d efinitions vga sequencer registers (i/o mapped) btv2115 brook t ree 64 bt character map select register name: seq_cfs index: 3c5h.03h, read/write size: 8 bit function: this register determine which character font will be used for display output. bit 7 of the text attribute byte determines whether the primary or secondary font is used. the bit contents of the character map select register are shown in table 36. table 37 and table 38 de?e the primary and secondary bits used to select font tables. this is only valid for text modes. text fonts are normally loaded into video buffer planes 2 or 3. the offset in the tables below refer to the offset from the base of plane 2 or 3. 3 map3 enable 0 = no write 1 = write allowed 2 map2 enable 0 = no write 1 = write allowed 1 map1enable 0 = no write 1 = write allowed 0 map0 enable 0 = no write 1 = write allowed table 36. character map select register bit function 7:6 reserved - hardwired to 00 5 secondary 0 4 primary 0 3 secondary 2 2 secondary 1 1 primary 2 0 primary 1 table 35. map mask register (2 of 2) bit function detail r egister d efinitions vga sequencer registers (i/o mapped) btv2115 brook t ree 65 bt table 37. secondary font selection bits 5,3,2 map selected plane offset 000 0 0k 001 1 16k 010 2 32k 011 3 48k 100 4 8k 101 5 24k 110 6 40k 111 7 56k table 38. primary font selection bits 4,1,0 map selected plane offset 000 0 0k 001 1 16k 010 2 32k 011 3 48k 100 4 8k 101 5 24k 110 6 40k 111 7 56k r egister d efinitions vga sequencer registers (i/o mapped) btv2115 brook t ree 66 bt memory mode register name: seq_mmode index: 3c5h.04h, read/write size: 8 bit function: this register controls miscellaneous setup features related to the video buffer and sequencer control. the bit contents of the memory mode register are shown in table 39. table 39. memory mode register bit function detail 7:4 reserved hardwired to 0h 3 chain 4 0 = normal addressing 1 = packed pixel mode; cpu address bits a1 and a0 determine which plane is accessed, and buffer address bits a3, a2 are replaced by cpu address bits a15, a14. 2 odd/even 0 = even cpu addresses access map0 and map2, odd cpu addresses access map1 and map3 1 = normal addressing 1 extended memory this bit only affects the odd/even addressing func- tionality controlled by chain odd/even bit in the vga graphics controller miscellaneous register. this bit never needs to be set to zero for btv2115 systems. 0 = 64kb of video memory 1 = 256kb of video memory for vga modes 0 reserved hardwired to 0 r egister d efinitions vga sequencer extension registers (i/o mapped) btv2115 brook t ree 67 bt vga sequencer extension registers (i/o mapped) unlock register name: seq_unlock index: 3c5h.06h, read/write size: 8 bit function: this register enables or disables access to the btv2115 extension reg- isters. if the extensions are unlocked, reading this register will return a status value. if the extensions are locked, reading this register will re- turn 0fh. the bit contents of the unlock register are shown in table 40. the btv2115 implements a context save restore mechanism in the vga block, that drastically reduces the i/o overhead for entering and leaving the interrupt- service routine. when 14h is written to the sequencer unlock register (3c5h.6), the current state is saved as follows: 1 copy current sequencer lock register value to a shadow byte4. 2 copy current graphics index register (3ce) to a shadow byte0. 3 copy gui_base0 to a shadow byte1. 4 copy gui_base1 to a shadow byte2. 5 copy gui_base2 to a shadow byte3. 6 force unlock state in sequencer 6 register table 40. sequencer unlock register bit function detail 7:5 reserved 4:0 unlock writing 12h to this ?ld unlocks the exten- sion registers. reads a 12h status. writing 14h to this ?ld saves vga context and unlocks the vga at interrupt service routine entry. reads a 14h status. writing 18h to this ?ld restores the vga context after an interrupt. reads back the previous status value (never contains 18h) r egister d efinitions vga sequencer extension registers (i/o mapped) btv2115 brook t ree 68 bt when 18h is written to the sequencer unlock register, the following occurs: 1 copy shadow byte 4 back to sequencer lock register 2 copy shadow byte 0 back to graphics index register 3 copy shadow byte 1 back to gui_base0 4 copy shadow byte 2 back to gui_base1 5 copy shadow byte 3 back to gui_base2 the isr input is as follows: 1 save sequencer index register 3c4h 2 write sequencer index to address the unlock and unlock, 6->3c4h 3 write save value (14h) to 3c5h (2ah and 2bh are one out16) 4 write to graphics index reg and gui_base0 (3ceh,3cfh) 5 write to graphics index reg and gui_base1 (3ceh,3cfh) 6 write to graphics index reg and gui_base2 (3ceh,3cfh) 7 read interrupt status through 000a0000h and process the return from isr is as follows: 1 write restore value (18h) to sequencer unlock register 2 restores unlock register and those shadowed graphics registers 3 restore sequencer index register 3c4h r egister d efinitions vga crt controller (i/o mapped) btv2115 brook t ree 69 bt vga crt controller (i/o mapped) the crt controller (crtc) uses indexed addressing to access the control reg- isters. the offset into the vga crtc data space is 3?5h, where ??is either b (3b5h) or d (3d5h) depending on whether the crt is monochrome or color, re- spectively. crtc color index name: crt_index_c port: 3d4h, read/write size: 8 bit function: this address accesses the crt_index register when vga miscella- neous output register bit 0 is set for a color display. this register con- tains the location of the register in the crtc block to be accessed by the next i/o read or write to the crt_data port. crtc monochrome index name: crt_index_m port: 3b4h, read/write size: 8 bit function: this address accesses the crt_index register when vga miscella- neous output register bit 0 is set for a monochrome display. this reg- ister contains the location of the register in the crtc block to be accessed by the next i/o read or write to the crt_data port. crtc color data name: crt_data_c port: 3d5h, read/write size: 8 bit function: this port allows access to one of the crt data registers, according to the value of the crt_index register. this register is accessible only for color, misc_out_r[0] = 1 (see table 64 on page 88). crtc monochrome data name: crt_data_m port: 3b5h, read/write size: 8 bit function: this port allows access to one of the crt data registers, according to the value of the crt_index register. this register is accessible only for monochrome, misc_out_r[0] = 0 (see table 64 on page 88). r egister d efinitions vga crt controller (i/o mapped) btv2115 brook t ree 70 bt horizontal total register name: crt_htot index: 3?5h.00h, read/write size: 8 bit function: this register sets the horizontal scan time and is loaded in terms of character time. it includes left and right borders, displayed characters, and horizontal retrace time (front porch, back porch, and sync pulse). if ? is the total line character count, then this register should be loaded with ?-5? horizontal display end register name: crt_hdsp_end index: 3?5h.01h, read/write size: 8 bit function: this register contains the number of displayed characters on a horizon- tal line, and is loaded in terms of character clocks. if ? is the character count, then this register should be loaded with ?-1? start horizontal blank register name: crt_hblank_st index: 3?5h.02h, read/write size: 8 bit function: this register contains the count at which horizontal blanking should begin. it is in terms of character clocks. if ? is the character count, then this register should be loaded with ?-1? end horizontal blank register name: crt_hblank_end index: 3?5h.03h, read/write size: 8 bit function: this register contains the count at which horizontal blanking should end, in terms of character clocks. if ? is the character count, then this register should be loaded with ?-1? the msb of the end horizontal blank ?ld is in the end horizontal sync register. together, these two registers specify only the least signi?ant 6 bits of the count at which blanking will end. the actual 8-bit count at which blanking will end is the ?st time after the start blanking count that the least signi?ant 6 bits of the character counter match these 6 bits. the bit contents of the end horizontal blank register are shown in table 41. r egister d efinitions vga crt controller (i/o mapped) btv2115 brook t ree 71 bt start horizontal sync register name: crt_hsync_st index: 3?5h.04h, read/write size: 8 bit function: this register contains the count at which the horizontal sync pulse should begin. it is in terms of character clocks. if ? is the character count, then this register should be loaded with ?-1? end horizontal sync register name: crt_hsync_end index: 3?5h.05h, read/write size: 8 bit function: this register contains the count at which the horizontal sync pulse should end. it is in terms of character clocks. if ? is the character count, then this register should be loaded with ?-1? this register spec- i?s only the least signi?ant 5 bits of the count at which the sync pulse will end. the actual 8-bit count at which it will end is the ?st time after the start horizontal sync count that the least signi?ant 5 bits of the character counter match these 5 bits. the bit contents of the end hor- izontal sync register are shown in table 42. table 41. end horizontal blank register bit function detail 7 compatible read this ?ld has no effect on btv2115 opera- tion. 6:5 display enable skew this ?ld has no effect on btv2115 opera- tion. 4:0 hblank <4:0> end horizontal blank count. the msb is in the end horizontal sync register. table 42. end horizontal sync register bit function detail 7 hblank 5 msb of hblank 6:5 reserved 4:0 hsync <4:0> least signi?ant 5 bits of start horizontal sync register plus the width of hsync in character clocks. r egister d efinitions vga crt controller (i/o mapped) btv2115 brook t ree 72 bt vertical total register name: crt_vtot index: 3?5h.06h, read/write size: 8 bit function: this register sets the number of scan lines in the frame. it contains the eight least signi?ant bits. the most signi?ant two bits are in the over?w register. if ? is the scan line count, then this register should be loaded with ?-2? over?w register name: crt_overflow index: 3?5h.07h, read only size: 8 bit function: this register contains miscellaneous over?w bits associated with oth- er vertical timing registers. the bit contents of the over?w register are shown in table 43. preset row scan register name: crt_pre_rs index: 3?5h.08h, read/write size: 8 bit function: this register is used for line scrolling. the bit contents of the preset row scan register are shown in table 44. table 43. over?w register bit function 7 start vsync 9 6 end vertical display enable 9 5 vertical total 9 4 line compare 8 3 start vblank 8 2 start vsync 8 1 end vertical display enable 8 0 vertical total 8 table 44. preset row scan register bit function detail 7 reserved hardwired to 0 6:5 byte pan this ?ld has no effect on btv2115 opera- tion. 4:0 preset row scan count specify scan line for 1st character row r egister d efinitions vga crt controller (i/o mapped) btv2115 brook t ree 73 bt character height register name: crt_cheight index: 3?5h.09h, read/write size: 8 bit function: this register speci?s the cell height for characters and also contains two over?w bits and the scan line double bit. the bit contents of the character height register are shown in table 45. cursor start register name: crt_cur_st index: 3?5h.0ah, read/write size: 8 bit function: this register sets the ?st scan line to display the cursor within the character cell which contains the cursor. it also turns the cursor off and on. the bit contents of the cursor start register are shown in table 46. cursor end register name: crt_cur_end index: 3?5h.0bh, read/write size: 8 bit function: this register sets the last scan line to display the cursor within the char- acter cell which contains the cursor. the bit contents of the cursor end register are shown in table 47. table 45. character height register bit function detail 7 scan double 0 = normal operation 1 = activate line doubling 6 line compare 9 over?w bit 5 start vblank 9 over?w bit 4:0 cell height number of scan lines / character table 46. cursor start register bit function detail 7:6 reserved hardwired to 00 5 cursor toggle 0 = cursor on 1 = cursor off 4:0 top of cursor starting scan line for cursor r egister d efinitions vga crt controller (i/o mapped) btv2115 brook t ree 74 bt start address high register name: crt_screen_sth index: 3?5h.0ch, read/write size: 8 bit function: this register sets the high order 8 bits of the 16-bit quantity which de- termines the frame buffer address of the upper left corner of the display screen. the start address is in terms of character positions. the actual frame buffer starting address is scaled by a factor of 1, 2, or 4 depend- ing on whether the byte, word, or double-word crt addressing mode is selected. see the crt mode control and crt underline register de?itions. start address low register name: crt_screen_stl index: 3?5h.0dh, read/write size: 8 bit function: this register sets the low order 8 bits of the 16-bit quantity which de- termines the frame buffer address of the upper left corner of the display screen. the start address is in terms of character positions. the actual frame buffer starting address is scaled by a factor of 1, 2, or 4 depend- ing on whether the byte, word, or double-word crt addressing mode is selected. see the crt mode control and crt underline register de?itions. cursor location high register name: crt_cur_loch index: 3?5h.0eh, read/write size: 8 bit function: this register sets the high order 8 bits of the 16-bit quantity that con- trols the cursor location. the location is in terms of character positions. it points to the character in the frame buffer which will contain the cur- sor. the actual frame buffer cursor address is scaled by a factor of 1, 2, or 4 depending on whether the byte, word, or double-word crt ad- dressing mode is selected. see the crt mode control and crt under- line register de?itions. table 47. cursor end register bit function detail 7 reserved hardwired to 0 6:5 cursor skew this ?ld has no effect on btv2115 opera- tion. 4:0 bottom of cursor ending scanline for cursor r egister d efinitions vga crt controller (i/o mapped) btv2115 brook t ree 75 bt cursor location low register name: crt_cur_locl index: 3?5h.0fh, read/write size: 8 bit function: this register sets the low order 8 bits of the 16-bit quantity that controls the cursor location. the location is in terms of character positions. it points to the character in the frame buffer which will contain the cur- sor. the actual frame buffer cursor address is scaled by a factor of 1, 2, or 4 depending on whether the byte, word, or double-word crt ad- dressing mode is selected. see the crt mode control and crt under- line register de?itions. start vertical sync register name: crt_vsync_st index: 3?5h.10h, read/write size: 8 bit function: this register determines the start of the vertical sync pulse. the scan line counter is compared to this register at each horizontal sync time. this register contains the lower 8 bits of this value. bits 8 and 9 are in the over?w register. if ? is the scan line count, then this register should be loaded with ?-1? end vertical sync register name: crt_vsync_end index: 3?5h.11h, read/write size: 8 bit function: this register determines the end of the vertical sync pulse. the hori- zontal scan line count is compared to the start vertical sync register. if the values are equal, a vertical sync pulse is ended. this register speci?s only the least signi?ant 4 bits of the 10-bit count at which the sync pulse will end. the actual count at which it will end is the ?st time after the start vertical sync count that the least signi?ant 4 bits of the line counter match these 4 bits. if ? is the scan line count, then this register should be loaded with ?-1? miscellaneous control ?lds are also supported in this register. the bit contents of the end vertical sync register are shown in table 48. r egister d efinitions vga crt controller (i/o mapped) btv2115 brook t ree 76 bt vertical display end register name: crt_vdsp_end index: 3?5h.12h, read/write size: 8 bit function: this register determines the number of scan lines displayed with frame buffer data. this register contains the lower 8 bits of the display end value. bits 8 and 9 are stored in the over?w register. if ? is the scan line count, then this register should be loaded with ?-1? offset register name: crt_offset index: 3?5h.13h, read/write size: 8 bit function: this register speci?s the pitch in bytes between adjacent character row or scan lines. the next row start address (dword address) equals the current row start address plus (k * value in offset register), where k has a value of 2 in byte mode, 4 in word mode, and 8 in dword mode. byte or word addressing is set by the crtc mode control register. underline register name: crt_underline index: 3?5h.14h, read/write size: 8 bit function: this register includes the scan line location for underlining characters and the double word addressing control bits. the bit contents of the underline register are shown in table 49. table 48. end vertical sync register bit function detail 7 crtc [7:0] write pro- tect 0 = enable writes to crt index registers 7:0h 1 = disable writes to crt index registers 7:0h, the line compare bit in the over- ?w register is not affected 6 reserved 5 enable vertical sync interrupt 0 = enable vertical sync interrupt 1 = disable vertical sync interrupt 4 clear vertical sync interrupt 0 = clear vertical sync interrupt 1 = allows vertical sync interrupt generation 3:0 vertical sync end scan line count to end vsync r egister d efinitions vga crt controller (i/o mapped) btv2115 brook t ree 77 bt start vertical blank register name: crt_vblank_st index: 3?5h.15h, read/write size: 8 bit function: this register determines the start of vertical blanking. the scan line counter is compared to this register. when the values are equal, vertical blank begins. the lower 8 bits are loaded in this register. bit 8 is stored in the over?w register and bit 9 is stored in the character height register. if ? is the scan line count, then this register should be loaded with ?-1? end vertical blank register name: crt_vblank_end index: 3?5h.16h, read/write size: 8 bit function: this register determines the end of vertical blanking. the scan line counter is compared to this register. when the values are equal, vertical blank ends. this register speci?s only the least signi?ant 8 bits of the 10-bit count at which the blanking period will end. the actual count at which it will end is the ?st time after the start vertical blank count that the least signi?ant 8 bits of the line counter match these 8 bits. if ? is the scan line count, then this register should be loaded with ?-1? mode control register name: crt_mode_ctl index: 3?5h.17h, read/write size: 8 bit function: this register controls several aspects of the display setup. the bit con- tents of the mode control register are shown in table 50. table 49. underline register bit function detail 7 reserved hardwired to 0 6 dword mode 0 = crt addresses frame buffer in byte or word mode 1 = crt addresses frame buffer in dword mode. 5 count by four 0 = crt increments frame buffer pointer on every character clock unless count-by-two bit in the crt mode control register is set. 1 = crt increments frame buffer pointer once every four character clocks 4:0 underline location scan line value within a character cell where the underline character is displayed. lines 1 through ? are speci?d by values 0 through ?-1? r egister d efinitions vga crt controller (i/o mapped) btv2115 brook t ree 78 bt line compare register name: crt_linecmp index: 3?5h.18h, read/write size: 8 bit function: this register is used for split screen operation. when the scan line counter equals the line compare value, the crt s frame buffer pointer is cleared causing the lines beneath the compare scan line to be updated from video buffer display location 0. the lower 8 bits are loaded in the line compare register. bit 8 is in the over?w register and bit 9 is lo- cated in the character height register. if ? is the scan line count, then this register should be loaded with ?-1? table 50. mode control register bit function detail 7 sync enable 0 = hsync and vsync inactive 1 = hsync and vsync active 6 word or byte mode this bit is overridden by the double-word mode bit in crt underline register. 0 = word mode - frame buffer address is incremented by two 1 = byte mode - frame buffer address is incremented by one 5 address wrap 0 = in word mode, memory address 14 appears at memory address 0 1 = select memory address 16 for odd/even mode when 256kb of video memory is present 4 reserved 3 count by two 0 = character clock increments memory address counter 1 = character clock/2 increments memory address counter 2 vertical count double 0 = vertical line counter increments once per hsync 1 = vertical line counter increments once every two hsync pulses, effectively dou- bling all vertical counts. 1 select row scan counter 0 = row scan counter bit 1 is output at mem- ory address 14 1 = bit 14 of the crtc address counter is out- put at memory address 14 0 compatibility mode 0 = row scan counter bit 0 is output for mem- ory address 13 1 = memory address bit 13 unchanged r egister d efinitions vga attribute controller (i/o mapped) btv2115 brook t ree 79 bt vga attribute controller (i/o mapped) the attribute controller uses indexed addressing to access twenty control regis- ters. sixteen of these registers are palette registers. the attribute controller uses a single i/o port at 3c0h to write both the index register and the data registers. read- ing the 3c0h address will always return the value of the index register. a second port is available at 3c1h to read the value of the indexed data register. the vga contains internal state which keeps track of whether the index or data registers will be accessed on the next write. each write access toggles the state be- tween index and data registers. the attribute controller register write mechanism can be reset to point to a known state. this is done by reading the input status #1 register (3xah). this resets the 3c0h write port to point to the index register. attribute index and data port name: att_addr port: 3c0h, read/write size: 8 bit function: this register can always be read at 3c0h. however, when writing to 3c0h, the state of the port toggles between writing to the index register and the data registers. the data register written to is determined by the value last written to the index register. if the state is unknown, issue a read of the input status #1 register (3xah) to re- set the port for writing the index register. bit 5 of this register must be a zero to allow the cpu to read or write the palette registers. otherwise, writes are ineffectual and reads return 3fh. also, if bit 0 is not set to one upon completing the palette modi?ations, then the vga refresh logic will not be able to access the palette and the screen will be all one color. the bit contents of the attribute index and data port register are shown in table 51. table 51. attribute index/data port register bit function detail 7:6 reserved hardwired to 00 5 video on 0 = cpu drives the palette address 1 = refresh logic drives the palette address 4:0 attribute index 0-fh palette registers 10h mode control 11h overscan color 12h color plane enable 13h horizontal panning 14h color select r egister d efinitions vga attribute controller (i/o mapped) btv2115 brook t ree 80 bt read data port name: att_rd port: 3c1h, read only size: 8 bit function: data registers are always read from the read data port. reading the data register does not affect the index register. the bit contents of the read data port register are shown in table 51. palette registers name: att_pal_reg[15:0] index: 3c0h.0fh-00h, read/write size: 8 bits each function: these 16 registers comprise the ega palette. in all bios modes, frame buffer color indices are translated to an output color index through this palette. the bit contents of the palette register are shown in table 53. mode control register name: att_mode index: 3c0h.10h, read/write size: 8 bit function: this register controls various attribute modes. the bit contents of the mode control register are shown in table 54. table 52. read data port register bit function 7:5 reserved 4:0 index to the data registers in the attribute controller block. table 53. palette registers bit function 7:6 reserved - hardwired to 00 5 secondary red 4 secondary green/intensity 3 secondary blue/mono 2 red 1 green 0 blue r egister d efinitions vga attribute controller (i/o mapped) btv2115 brook t ree 81 bt overscan color register name: att_ovrs index: 3c0h.11h, read/write size: 8 bit function: the overscan color register sets the color for the border area of the dis- play. for monochrome displays this register is set to 0. table 54. mode control register bit function detail 7 video select 0 = bits 4 and 5 of the palette registers are used as address bits 1 = color select register <1:0> are used as address bits 6 pel width this bit determines how pixels are assembled at the output of the ega palette. when zero, the six- bit output of the ega palette is sent on every pixel clock. when one, the least signi?ant 4-bits of ega palette output from two consecutive pixel clocks are assembled into one 8-bit quantity. this 8-bit value is then sent to the dac for two consecutive clocks. 0 = normal mode 1 = 256 color mode 5 pixel pan 0 = a line compare has no effect on pixel panning 1 = a line compare terminates pixel panning for remainder of frame. 4 reserved hardwired to 0 3 blink/intensity 0 = blink inactive, set background intensity 1 = blink active 2 line graphics enable 0 = the 9th bit of a 9 pixel character will be the same as the background 1 = the 9th bit of a 9 pixel character will be the same as the 8th bit for character code between c0-dfh 1 display type this bit only effects graphics mode blinking. 0 = color display attributes 1 = monochrome attributes 0 mode enable 0 = text mode 1 = graphics mode r egister d efinitions vga attribute controller (i/o mapped) btv2115 brook t ree 82 bt color plane enable register name: att_cpe index: 3c0h.12h, read/write size: 8 bit function: this register enables the four planes into the palette registers. this register also sets the inputs for the diagnostics bits in the input status #1 register. the bit contents of the color plane register are shown in table 55. horizontal panning register name: att_hpan index: 3c0h.13h, read/write size: 8 bit function: this register is available for text or graphics modes and speci?s the number of pixels the display data will be shifted left horizontally. in text mode, characters can be shifted left one pixel less than the cell width. in 256 color modes, up to 3 position pixel shifts may occur. the bit contents of the horizontal panning register are shown in table 56 and the allowable pixel pans are shown in table 57. table 55. color plane enable register bit function detail 7:6 reserved hardwired to 00 5:4 video status mux 00 = input status #1[5:4] = p2-red, p0-blue 01 = input status #1[5:4] = p5-secondary red, p4- secondary blue 10 = input status #1[5:4] = p3-secondary blue, p1- green 11 = input status #1[5:4] = p7, p6 (256-color modes only) see table 63 on page 87. 3 enable plane 3 0 = disable plane, force pixel bit to 0 before addressing palette 1 = enable color plane 2 enable plane 2 see bit 3 1 enable plane 1 see bit 3 0 enable plane 0 see bit 3 table 56. horizontal panning register bit function 7:4 reserved - hardwired to 0h 3:0 pixel pan amount r egister d efinitions vga attribute controller (i/o mapped) btv2115 brook t ree 83 bt color select register name: att_clrsel index: 3c0h.14h, read/write size: 8 bit function: this register contains two ?lds used to select locations in the video dac. the bit contents of the color select register are shown in table 58. table 57. allowable pixel pans pixel pan amount 9 bit character 8 bit character 256 color mode 010 0 121 -- 232 1 343 -- 454 2 565 -- 676 3 787 -- 8-fh 0 -- -- table 58. color select register bit function detail 7:4 reserved hardwired to 0h 3:2 color bits[7:6] these bits are concatenated with the lower 6 bits from the palette registers to form an index into the video dac. these bits are ignored in 256 color modes. 1:0 color bits[5:4] if attribute controller mode register <7> =1, these bits replace the corresponding bits in the palette registers to form an index into the video dac. otherwise, these bits are ignored. these bits are ignored in 256-color modes. ese bits are ineffective in 8, 16, and 24 bpp modes. r egister d efinitions vga general / external registers (i/o mapped) btv2115 brook t ree 84 bt vga general / external registers (i/o mapped) the btv2115 has seven general registers. the ?lds in this register block includes motherboard/adapter handshake during boot or switching of video display, clock frequency selection, sync signal polarity selection, and general-purpose status. all of these registers are directly accessible from the i/o bus. pos102 register name: mca_pos port: 102h, read/write size: 8 bit function: the pos102 register contains a bit which wakes up the vga in con- junction with the adapter sleep register enable bit. when the vga is in the wakeup state, the btv2115 may respond to bus cycles to vga address space. this register is accessible only if the btv2115 is con?- ured as an adapter and the setup bit is set in the adapter sleep register. the bit contents of the pos102 register are shown in table 59. see the con?uration registers section for information about how to con?ure the chip as an adapter versus a motherboard and how to con?ure the reset state of the sleep registers. adapter sleep register name: adapt_sleep port: 46e8h, read/write size: 8 bit function: the adapt_sleep register contains a bit which wakes up the vga in conjunction with the pos102 wakeup vga bit. when the vga is in the wakeup state, the btv2115 may respond to bus cycles to vga ad- dress space. this register is accessible only if the btv2115 is con?- ured as an adapter vga. the setup bit is used to enable access to the pos102 register. the bit contents of the adapter sleep register are shown in table 60. table 59. pos102 register bit function detail 7:1 reserved hardwired to 0 0 wakeup vga 0 = vga is disabled 1 = vga is enabled to respond to vga bus cycles if the enable bit is set in the adapter sleep register r egister d efinitions vga general / external registers (i/o mapped) btv2115 brook t ree 85 bt the protocol for enabling an adapter vga is the following: 1. enable pos102 setup. write 18h to adapter sleep. 2. set wakeup vga bit in pos102 register. write 01h to pos102. 3. turn off pos102 setup. write 08h to adapter sleep. refer to grp_cfg3[5] in table 23 on page 52 for information about how to con?ure the chip as an adapter versus a motherboard and how to con?ure the re- set state of the sleep registers. motherboard sleep register name: mbd_sleep port: 3c3h, read/write size: 8 bit function: this register can be accessed only if the btv2115 is con?ured as a motherboard vga. the bit contents of the motherboard sleep register are shown in table 61. refer to grp_cfg3[5] in table 23 on page 52 for information about how to con- ?ure the chip as an adapter versus a motherboard and how to con?ure the reset state of the sleep registers. table 60. adapter sleep register bit function detail 7:5 reserved hardwired to b?00 4 setup 0 = pos102 write access is disabled 1 = pos102 write access is enabled, vga access is disabled. 3 enable subsystem 0 = btv2115 is disabled 1 = btv2115 is enabled to accept vga bus cycles if the pos102 register wakeup vga bit is set. 2:0 reserved hardwired to b?00 table 61. motherboard sleep register bit function detail 7:1 reserved hardwired to 0 0 enable subsystem 0 = btv2115 is disabled from accepting vga bus cycles 1 = btv2115 is enabled to accept vga bus cycles r egister d efinitions vga general / external registers (i/o mapped) btv2115 brook t ree 86 bt input status #0 register name: inp_stat0 port: 3c2h, read only size: 8 bit function: the input status #0 register contains the vertical retrace interrupt bit. the bit contents of the input status #0 register are shown in table 62. color input status #1 register name: inp_stat_c port: 3dah color, read only size: 8 bit function: this register contains assorted status bits. reading this register resets the state of the attribute controller index/write port for color systems to 3c0h. the bit contents of the input status #1 register (for both color and monochrome) are shown in table 63. this register is accessible only if misc_out_r[0] = 1 (see table 64 on page 88). monochrome input status #1 register name: inp_stat_m port: 3bah, read only size: 8 bit function: this register contains assorted status bits. reading this register resets the state of the attribute controller index/write port for monochrome systems to 3c0h. the bit contents of the input status #1 register (for both color and monochrome) are shown in table 63. this register is ac- cessible only if misc_out_r[0] = 0 (see table 64 on page 88). table 62. input status #0 register bit function detail 7 vertical retrace inter- rupt 0 = interrupt cleared 1 = interrupt pending 6:5 reserved hardwired to b?0 4 monitor detection this ?ld is unde?ed. monitor status is available by accessing registers on the pacdac device. 3:0 reserved hardwired to 0h r egister d efinitions vga general / external registers (i/o mapped) btv2115 brook t ree 87 bt write miscellaneous output register name: misc_out_w port: 3c2h, write only size: 8 bit function: this register contains write only ?lds related to setting up the vga environment. the bit contents of the miscellaneous output registers (for both write and read) are shown in table 64. what is written here is read at 3cch. read miscellaneous output register name: misc_out_r port: 3cch, read only size: 8 bit function: this register contains several read only ?lds related to setting up the vga environment. the bit contents of the miscellaneous output reg- isters (for both write and read) are shown in table 64. table 63. input status #1 register bit function detail 7:6 reserved hardwired to b?0 5:4 video status mux multiplexed video bits as selected by bits 5:4 of the attribute controller color plane enable register. 00 = p2, p0 01 = p5, p4 10 = p3, p1 11 = p7, p6 see table 55 on page 82 3 vertical retrace status 0 = vertical retrace inactive 1 = vertical retrace active 2:1 reserved hardwired to b?0 0 display enable status 0 = display active 1 = display inactive-horizontal or vertical retrace active r egister d efinitions vga general / external registers (i/o mapped) btv2115 brook t ree 88 bt feature control register name: fc port: 3cah read 3xah write: 3bah if misc_out_r[0] = 0 (mono), or 3dah if misc_out_r[0] = 1 (color) size: 8 bit function: the feature control functionality does not add any capability to btv2115 system and is not supported. table 64. miscellaneous output register (read and write) bit function detail 7 vsync polarity a 0 = active high 1 = active low 6 hsync polarity a 0 = active high 1 = active low 5 page select this bit determines affects the value used as the least signi?ant bit in odd/even addressing modes. it is for diagnostic use, and should be set to one for normal use. 4 reserved hardwired to 0 3:2 clock select [1:0] 00 = select 25.180 mhz pixel clock 01 = select 28.325 mhz pixel clock 10 = pixel clock rate determined by pll value written to media buffer 11 = reserved 1 enable frame buffer access 0 = disable cpu access to vga frame buffer 1 = enable cpu access to vga frame buffer 0 crtc i/o address 0 = select monochrome - 3bh 1 = select color - 3dh a. monitors select their vertical scan rate and gain based on hsync and vsync polarity, which is set by bits <7:6> . the selection is as follows: 0 = reserved 1 = 400 line mode 2 = 350 line mode 3 = 480 line mode r egister d efinitions vga color registers (i/o mapped) btv2115 brook t ree 89 bt vga color registers (i/o mapped) the btv2115 supports the 5 vga dac registers (color registers) in addition to the dac alias registers in the graphics controller extended address space. fol- lowing is a description of the vga dac registers. dac mask register name: dac_mask port: 3c6, read/write size: 8 bit function: this 8-bit register contains a bit mask of the pixel value going to the dac lookup table (vga palette, or color registers). a ? enables the corresponding bit, while a ? forces the bit to zero before it addresses the color lookup table. this register does not affect access to the color palette through the 3cxh cpu ports. it only affects the pixel value coming from the attribute logic for display on the screen. this register is normally not written by application code but initialized by bios or device drivers to establish the color lookup table. dac state register name: dac_state port: 3c7h, read only size: 8 bit function: this register shows whether the dac data read/write port is in a read or write mode, depending on whether the dac read address register or dac write address register was written to most recently. the bit contents of this register are shown in table 65. dac read address register name: dac_rdaddr port: 3c7h, write only size: 8 bit function: this register contains an 8 bit address used to select one of 256 video dac color registers during a read operation. the next three reads of the dac data register will return three 6-bit values for red, green, and blue settings, respectively. after the blue value is read, the val- table 65. color registers: dac state register bit function detail 7:2 reserved hardwired to b?00000 1:0 state 00 = write mode 11 = read mode r egister d efinitions vga color registers (i/o mapped) btv2115 brook t ree 90 bt ue in the dac read address register is incremented to point to the next dac color register. this feature allows the programmer to read all 768 values from the dac without updating the index value in the dac write address register. this value will also wrap from 255 to 0. the dac read address can be written with another value at any time be- tween each set of three reads to the dac data register. dac write address register name: dac_wraddr port: 3c8h, read/write size: 8 bit function: this register contains an 8 bit address used to select one of 256 video dac color registers during a write operation. the next three writes to the dac data register will output three 6-bit values for red, green, and blue settings, respectively. after the blue value is output, the value in the dac write address register is incremented to point to the next dac color register. this feature allows the programmer to output all 768 values to the dac without updating the index value in the dac write address register. this value will also wrap from 255 to 0. the dac write address register can be written with another value at any time between each set of three writes to the dac data register dac data register name: dac_data port: 3c9h, read/write size: 8 bit function: this register is used to read or write 18 bits of palette data depending on the mode of operation. writes to the dac read address register put this register in the read mode, while writes to the dac write address register put this register in the write mode. data access to and from this register is in groups of three bytes. each byte con- tains the 6-bit palette value for the dac output signal. the ?st byte contains the red signal value, the second byte contains the green signal value, and the third byte contains the blue signal value. on reads, the most signi?ant two bits of each byte are always set to ?? r egister d efinitions legacy audio fm registers (i/o mapped) btv2115 brook t ree 91 bt legacy audio fm registers (i/o mapped) the btv2115 provides i/o mapping for the legacy audio fm register space. pro- vided speci?ally to support the yamaha opl3 fm synthesizer, this i/o interface indirectly addresses the opl3 s internal registers. for speci? register descrip- tions, refer to the yamaha ymf-262 product information bulletin. the i/o decoder is enabled by setting bit 7 of the legacy audio emulation reg- ister. select either i/o base address 022xh or 024xh by setting bit 6 of the legacy audio emulation register (default is 022xh). additionally, a memory mapped interface supports opl3 and opl4 (ymf278- f) device communications. refer to ?amaha support?on page 120. this section provides register addressing information for the opl3 device. be- low, table 66 summarizes the legacy audio fm register addresses. note legacy audio supports the yamaha 2 and 4 operator mode fm synthesizer chip family. the opl3 i/o address space is a superset of the opl2 s address space; thus opl2 (ym3812) interface support is implied. table 66. legacy audio fm register addresses legacy audio emulation register bit 6 = 0 legacy audio emulation register bit 6 = 1 i/o addr register type i/o addr register type 388 bank0 address 388 bank0 address 389 bank0 data 389 bank0 data 38a bank1 address 38a bank1 address 38b bank1 data 38b bank1 data 220 bank0 address 240 bank0 address 221 bank0 data 241 bank0 data 222 bank1 address 242 bank1 address 223 bank1 data 243 bank1 data 228 bank0 address 248 bank0 address 229 bank0 data 249 bank0 data notes: 1. the opl3 uses both bank 0 and bank 1, opl2 uses only bank 0 r egister d efinitions legacy audio fm registers (i/o mapped) btv2115 brook t ree 92 bt opl bank 0 address name: adlib_bnk0_addr port: 0388h, read/write name: opl3_bnk0_addr2 port: 0220h, read/write name: opl2_bnk_addr2 port: 0228h, read/write name: opl3_bnk0_addr4 port: 0240h, read/write name: opl2_bnk_addr4 port: 0248h, read/write size: 8 bit function: this register is the yamaha opl3 bank 0 address port. the value writ- ten into this register provides an offset into the opl3 register space. additionally, this register provides opl3 status information when read. this register does not auto-increment. opl bank 0 data name: adlib_bnk0_data port: 0389h, write only name: opl3_bnk0_data2 port: 0221h, write only name: opl2_bnk_data2 port: 0229h, write only name: opl3_bnk0_data4 port: 0241h, write only name: opl2_bnk_data4 port: 0249h, write only size: 8 bit function: this register is the yamaha opl3 bank 0 data port. the value written into this register is placed into an opl3 internal register whose offset is determined by the current bank 0 address port value. read-back is not available. r egister d efinitions legacy audio fm registers (i/o mapped) btv2115 brook t ree 93 bt opl bank 1 address name: adlib_bnk1_addr port: 038ah, read/write name: opl3_bnk1_addr2 port: 0222h, read/write name: opl3_bnk1_addr4 port: 0242h, read/write size: 8 bit function: this register is the yamaha opl3 bank 1address port. the value writ- ten into this register provides an offset into the opl3 register space. additionally, this register provides opl3 status information when read. this register does not auto-increment. opl bank 1 data name: adlib_bnk1_data port: 038bh, write only name: opl3_bnk1_data2 port: 0223h, write only name: opl3_bnk1_data4 port: 0243h, write only size: 8 bit function: this register is the yamaha opl3 bank 0 data port. the value written into this register is placed into an opl3 internal register whose offset is determined by the current bank 0 address port value. read-back is not available. r egister d efinitions legacy audio mixer registers (i/o mapped) btv2115 brook t ree 94 bt legacy audio mixer registers (i/o mapped) the btv2115 provides i/o mapping for the legacy audio mixer registers. the mixer is controlled by a series of indirectly addressed 8-bit registers. these regis- ters are accessed by the following mixer address/ mixer data ports. the i/o de- coder is enabled by setting bit 7 of the legacy audio emulation register. select either i/o base address 022xh or 024xh by setting bit 6 of the legacy audio em- ulation register. mixer address name: la_mix_addr2 port: 0224h, write only name: la_mix_addr4 port: 0244h, write only size: 8 bit function: this write only register provides an offset into the internal register mapping of the legacy audio mixer registers. mixer data name: la_mix_data2 port: 0225h, read/write name: la_mix_data4 port: 0245h, read/write size: 8 bit function: the value written into this register is placed into a legacy audio mixer internal register whose offset is determined by the current mixer ad- dress port value. r egister d efinitions legacy audio dsp registers (i/o mapped) btv2115 brook t ree 95 bt legacy audio dsp registers (i/o mapped) the btv2115 provides i/o mapping for the legacy audio dsp registers used for digitized voice audio playback and record. these registers are comprised of a reset register, read data port, command data port/command status port, and a read data status port. the i/o decoder is enabled by setting bit 7 of the legacy audio emu- lation register. select either i/o base address 022xh or 024xh by setting bit 6 of the legacy audio emulation register. dsp reset name: la_dsp_reset2 port: 0226h, write only name: la_dsp_reset4 port: 0246h, write only size: 8 bit function: this write only register is provided for resetting the legacy audio sub- system. dsp read data name: la_dsp_read2 port: 022ah, read only name: la_dsp_read4 port: 024ah, read only size: 8 bit function: this read only register provides either command response data or re- corded audio data. the dsp read status register is polled for valid data ready. dsp command-data / command status name: la_dsp_cmd2 port: 022ch, read/write name: la_dsp_cmd4 port: 024ch, read/write size: 8 bit function: this register provides digitized voice control commands or digitized voice data when written. the read-back function of this register is polled for the command interface ready to write condition. r egister d efinitions audio registers (memory mapped) btv2115 brook t ree 96 bt dsp read status name: la_ready2 port: 022eh, read only name: la_ready4 port: 024eh, read only size: 8 bit function: this read only register provides the status of the dsp read data port. audio registers (memory mapped) the audio registers are de?ed starting on page 276 of ?udio subsystem? in the ?udio interface?chapter. gui aperture registers (memory mapped) the gui aperture space registers are de?ed as follows: guireg_fifo register: ?ui fifo register?on page 112. guireg_depth register: ?ui fifo depth register?on page 114. guireg_mba register: ?ba control register?on page 125. gui accelerator registers (memory mapped) the gui accelerator registers are de?ed starting in?ui registers?on page 172. video input registers (memory mapped) the video input registers are de?ed starting on in ?uffer management hard- ware?on page 256 in the ?ideo input subsystem?chapter. brook t ree 97 bt cpu a ddress s pace a pertures introduction this section describes the programming interface to the btv2115 media accelera- tor, the media buffer access ( mba) unit, the audio subsystem, the flash rom and the yamaha opl fm synthesizer. as in conventional vga systems, there is a cpu bus aperture at 000a0000h through 000bffffh through which the vga frame buffer is accessed, which we shall call the real mode aperture. in addition, in vl-bus con?urations, there is an optional aperture at 000c0000h which can be used for vga rom access, known as the vgarom aperture. in pci con?ura- tions, the vgarom aperture becomes the pci expansion rom aperture and can be moved to any 16mb boundary. the design assumes that the btv2115 is at- tached to the cpu via either a vl-bus or pci-bus. furthermore it is assumed that the gui and mba are accessed from protected mode well above the base memory of the system through the protected mode aperture. the protected mode aperture occupies 32mb of vl or pci bus address space beginning at the address speci?d in the gui base address register, as shown in figure 4. cpu a ddress s pace a pertures introduction btv2115 brook t ree 98 bt bits 31:25 of the hardware register gui_base, determine where the 32mb protected mode aperture resides in cpu address space. these seven bits, known as the protected mode base ?ld (pm_base), are matched against bits 31:25 of the vl/pci cpu address to determine when the protected mode aperture is accessed. the protected mode aperture must be offset from zero to prevent the protected mode aperture from overwriting any part of the 1mb of main memory reserved for the operating system from 00000000h to 000fffffh. to do this, at least one bit in the pm_base must be set to ??in order to specify a valid protected mode aper- ture address. in addition, gui_base[24] (pm_enable ?ld) is an overall en- able for the protected mode aperture and must be set to 1 to enable the protected mode aperture. consequently, gui_base[31:24] must be between 03h and ffh and must be odd so that the pm_base will contain 7?0000001 through 7 b1111111 thus allowing the protected mode aperture to be placed at any one of 127 possible 32mb blocks of cpu address space. figure 4. cpu apertures on a vl system ffffffffh gbase gbase+ 32mb -1 00000000h protected aperture cpu address space mode 000a0000h 000bffff real mode aperture 000fffffh protected mode real mode 000c7fffh vga rom 000c0000h aperture cpu a ddress s pace a pertures introduction btv2115 brook t ree 99 bt assume for the purposes of this discussion that the protected mode aperture starts at ac000000h so that the ?st byte in the aperture is accessed at ac000000h. thus the value to load into gui_base[31:24] is adh. therefore the placement of the aperture is constrained on 32mb boundaries. notice that the gui base address is speci?d in a vga style register. since two vgas can be supported in the sys- tem one can have two gui accelerators residing at two different base addresses. in essence, the 32mb aperture can be placed at address space a where 32mb a 4gb-32mb such that a is evenly divisible by 32m. in this manual, the offset to the protected mode is indicated by oring the speci?d addresses with an address constant, gbase, which is de?ed as follows: gbase[31:25] are set ex- actly equal to the pm_base in gui_base[31:25] while gbase[24:0] are set to zero. thus if gui_base[31:24] are set to 8?ad then gbase would have the value 32?ac000000. to form a cpu bus address, the programmer must ensure that segments and base registers of the cpu are set so that bits 31:25 of the cpu bus will match gbase[31:25] for accesses destined for the protected mode aper- ture. in c this would be coded: #define gbase 0xac000000l because the hardware will match cpu address bits [31:25] against the pm_base to detect a protected mode aperture access. one must distinguish gbase which is a programming constant or variable from the pm_base, which is a 7 bit ?ld in the 32-bit hardware gui_base reg- ister. these two values must be distinguished from grp_gui_base[3:0], which are the four extended vga graphics register indices placed in grp_index to read or write bytes within the gui_base register. notice that some differences exist between the apertures on a vl system versus a pci system. as shown in figure 5, for pci-bus the rom aperture is relocated to high memory (protected mode). it is the system bios responsibility to copy the vga bios from this high memory location to system ram and map it to 000c0000h to 000c7fffh. pci systems should never enable the rom hole. in pci con?urations, the gui_base register is actually loaded via pci con- ?uration space writes to the base address register 0 of con?uration space zero. see ?pu apertures in a pci-bus environment?on page 130. notice that pci bios places some restrictions on gbase. see ?ci constraints on gbase?on page 130. reminder the identi?rs gui_base, grp_gui_base, and gbase refer to different entities (as stated above). cpu a ddress s pace a pertures introduction btv2115 brook t ree 100 bt figure 5. cpu apertures on a pci system ffffffffh gbase gbase+ 32mb -1 00000000h protected aperture cpu address space mode 000a0000h 000bffffh real mode aperture 000fffffh protected mode real mode 000c7fffh expansion 000c0000h aperture expansion rom addr rom prefetch aperture pci_pref_base pci_pref_base+32mb-1 cpu a ddress s pace a pertures protected mode aperture btv2115 brook t ree 101 bt protected mode aperture cpu accesses are applied to the host interface module whether via vesa vl bus or pci bus. the host interface gives rise to an internal 3-state bus called the hbus. a number of chip subsystems or functional ?gents?are attached to the hbus, such as the vga controller, the audio subsystem, the gui accelerator, etc., as shown in figure 6. the protected mode aperture provides access to any of the functional agents except the vga. for this reason, devices on the vga extension bus are not accessible through the protected mode aperture. figure 7 shows how the 32mb protected mode aperture is broken into four 8mb maps. through the lowest addressed map passes all commands and data des- tined for the gui accelerator. the other three maps provide different views of the 4mb media buffer. btv2115 supports up to 4 mb of vram media buffer memory. each map could have been speci?d at 4 mb , however to do 1280x1024x32 requires 8 mb of vram , therefore btv2115 has been architected for an upgrade path to 8 mb media buffers. looking at the example addresses in figure 7, the map from ac800000h to acffffffh is a direct mapping of the media buffer. the map from ad000000h to ad7fffffh, called the flippin map, also completely maps the media buffer; however, bit, byte, and word data swapping is allowed in this region. the map from ad800000h to adffffffh is known as the funky map. the funky map can provide many different views of the media buffer. figure 6. hbus agents h ost i nterface pci/vl a udio vga c ontroller gui a ccelerator m edia b uffer a ccess y amaha f lash h ost b us vga e xtension b us c onfig i 2 c sct fm s ynth rom cpu a ddress s pace a pertures protected mode aperture btv2115 brook t ree 102 bt three media buffer maps are a distinct advantage over other gui accelerators, particularly when multimedia audio and video are supported in the media buffer. having the ability to support data bus steering for word, byte, and bit ?pping is a distinct advantage for supporting arbitrary image formats. such steering is con- trolled from deep within the windows device driver. such modes make supporting both little endian and big endian systems practical from a single controller design. direct map the direct map covers all of the media buffer memory and gives a clean, unmod- i?d view of all of the vram media buffer. addresses beyond 4mb in the 8mb map wrap back onto the actual 4mb (or less) vram. figure 7 depicts the direct map covering the vram. bytes, bits, and words are in their natural 486 little en- dian order with the least signi?ant byte in the 486 eax register mapping to the left most pixel position when a dword move instruction is used. no word, byte, or bit steering is performed on this direct map so regardless of settings in the win- dows driver for the flippin map devices and modules that wish to see an unmod- i?ble little endian view of the vram can always do so through the direct map. figure 7. protected mode aperture mapping to vram gbase gbase+8 mb gbase+16 mb gbase+24 mb funky map flippin map direct map gui command/ 4 mb vram register map gbase+32 mb adffffffh ad800000h ad000000h acffffffh ac800000h ac000000h 00000000h example addresses ad7fffffh ac7fffffh cpu a ddress s pace a pertures protected mode aperture btv2115 brook t ree 103 bt figure 8 shows that the cpu address bits 31:25 must match gui_base bits 31:25 (pm_base) for a protected mode aperture access to be accepted. once ac- cepted, cpu address bits 24:2 are passed to the internal hbus, shown in figure 6. in the media buffer access module hbus address bits 24:20 are decoded to deter- mine the type of access to perform. when the direct map is selected, cpu address bits 21:2 are passed directly to the internal mbus for use as a vram address. thus, cpu address bits 24:23 must equal 2?01 for the direct map to be selected. since only a maximum 4mb vram is supported in the btv2115 notice that cpu address bit 22 is a don t care. finally notice that cpu address bits 21:2, in conjunction with the cpu byte en- ables determine which byte(s) of the vram media buffer are accessed through the direct map. because the entire vram memory is accessible through the pro- tected mode aperture without having to resort to any page register mechanism, it is referred to as having a at view?of the media buffer. if we de?e a c constant to reference the direct map it could be coded: #define mba_direct 0x00800000l to access byte 100 hex within the direct map we could form an address such as: ((char *)(gbase | mba_direct | 0x00000100l)). having a separate map that is unchangeable is useful for multimedia accelera- tors that reside on the pci; such audio dsps need ?nmutilated?access to the au- dio in and out fifos in the media buffer. similarly a pci-resident hardware video codec can get ?nmutilated?access to the video in and video out buffers in the me- dia buffer. notice that address bit 22 is unconnected in btv2115 and is reserved for future expansion. cpu a ddress s pace a pertures protected mode aperture btv2115 brook t ree 104 bt software video codecs reside in different driver modules from the windows driver code. by offering both a funky map and a flippin map then these two code modules can be written to be totally oblivious to the internal drawing state of each other. figure 8. media buffer access via direct map gbase gbase+8 mb gbase+16 mb gbase+24 mb funky map flippin map direct map gui commands vram media buffer cpu access cpu address space 0 1 2 21 24 31 23 22 . . . . . . 25 gui_base mba direct 0 31 cpu address hbus address/control 4m 8m 32m 0 1 2 21 . . . mbus address/control 4m 0 1 map gbase[31:25] x 4 mb address 24 25 23 22 21 1 2 match protected mode accessed cpu a ddress s pace a pertures protected mode aperture btv2115 brook t ree 105 bt flippin map the flippin map covers all of the media buffer memory and gives a ?t view of all of the vram media buffer. however, unlike the direct map, the windows driver can control the data path steering in btv2115 so that bits can be swapped within a byte, bytes can be swapped within a word, or words can be swapped with- in a dword. addresses beyond 4mb in the 8mb map wrap back onto the actual 4mb (or less) vram. figure 9 depicts the flippin map covering the vram. in a fashion similar to the direct map, notice that the cpu address bits 31:25 must match the gui_base register bits 31:25 (pm_base) for a protected mode aperture access to be detected. similarly, cpu address bit 22 is a don t care. notice that cpu ad- dress bits 24:23 must equal 2?10 for the flippin map to be selected. cpu address bits 21:2 are passed to the mbus and ultimately to the memory controller in an unmodi?d way. the flippin map word and byte ?p bits in guireg_mba can cause the data path byte lanes and the byte enables to be re- ordered to effect a byte or word swap within a dword. finally, the guireg_mba flippin map bit ?p bit can cause the data path to bit reverse the word being written or read from the vram. if we de?e a c con- stant to reference the flippin map it could be coded: #define mba_flippin 0x01000000l to access byte 200 hex within the flippin map we could form an address such as: ((char *)(gbase | mba_flippin | 0x00000200l)) the same byte of vram can be accessed through either the direct map or the flippin map; however, the dwords viewed through the flippin map may have dif- ferent orderings of bits, bytes, words, within a dword than the same dword viewed through the direct map. notice that address bit 22 is unconnected in btv2115 and is reserved for future expansion. cpu a ddress s pace a pertures protected mode aperture btv2115 brook t ree 106 bt figure 9. protected mode aperture accessing vram via flippin map gbase gbase+8 mb gbase+16 mb gbase+24 mb funky map flippin map direct map gui commands vram media buffer cpu access cpu address space mba flippin note: data path steering can cause bit, byte, word, and/or dword ?pping. map 0 1 2 21 24 31 23 22 . . . . . . 25 gui_base 0 31 cpu address hbus address/control 1m 8m 32m 0 1 2 21 . . . mbus address/control 1m 4m 1 0 gbase[31:25] x 4 mb address 24 25 23 22 21 1 2 match protected mode accessed flipper straight cpu a ddress s pace a pertures protected mode aperture btv2115 brook t ree 107 bt funky map the funky map covers all of the media buffer memory and gives an alternate view of all of the vram media buffer. if we de?e a c constant to reference the funky map it could be coded: #define mba_funky 0x01800000l to access byte 100 hex within the funky map we could form an address such as: ((char *)(gbase | mba_funky | 0x00000100l)) the funky map provides some hardware assistance for soft video encoding. the video output driver supplies y and uv components to the funky map in this mode and the funky map modulates them with a quadrature sin/cos table to pro- duce a portion of a composite ntsc or pal pcm (pulse code modulated) wave- form. the funky map functionality is controlled by registers within the non-queued gui address space, see section?ui command/register map?on page 112 for further information. the programming interface includes several registers acces- sible from the non-queued gui command/register map. these registers include ?ui fifo register?on page 112, ?ui fifo depth register?on page 114 and the ?ba control register?on page 125. funky map support for sev to enable the funky map support of software encoded video (sev), guireg _mba [23] (modul_en) must be set to ?.?the funky map imple- ments the ntsc and pal quadrature modulation function to speed up the process of encoding a sev signal. in essence, the funky map implements the expressions: composite = y + usin(i) + vcos(i) and composite = y -usin(i) - vcos(i). the hard- ware stores these results as 16 composite samples for each uv sample and four composite samples for each y value presented. the y values are interpolated. hardware maintains an i counter for addressing the usinvcos look-up table. all modulation cpu bus cycles are write cycles for maximum through-put. cpu read cycles are treated as component access reads regardless of the setting of modul_en. in the sev mode, software writes to the funky map are as shown in figure 10. for each 32 bit composite plus or composite minus write cycle the cpu generates, a total of four dwords in vram are modi?d with quadrature modulation data. for each 32 bit uv write the cpu generates in ntsc mode the cpu should sup- ply two 32 bit composite plus and two 32 bit composite minus operations. the uv write operation causes 8 dwords of usin/vcos data to be burst read from vram. thus for each uv write operation a total of 32 bytes of usin/vcos data will be read. cpu a ddress s pace a pertures protected mode aperture btv2115 brook t ree 108 bt table 67 shows that when writing u/v values, u goes in vl/pci data bus [7:0] and v goes into vl/pci data bus [15:8]. the composite index register is incre- mented after a write u/v cycle. this is a post increment, occurring after the 16u i and 16v i values have been fetched. figure 10. funky map sev hbusaddr[22:21] = 00 => write u,v (causes table lookup and post increments i counter) hbusaddr[22:21] = 01 => composite plus (write 4x y+usin+vcos) hbusaddr[22:21] = 10 =>write composite index i hbusaddr[22:21] =11 => composite minus (write 4x y -usin -vcos) mba funky map 0 1 2 24 31 23 22 21 20 . . . . . . 25 gui_base 0 31 cpu address hbus address/control 8m 32m 0 1 2 21 . . . mbus address/control 1m 4m 1 1 gbase[31:25] 1 mb address 24 25 23 22 21 1 2 match protected mode accessed 0 31 cpu data bus 0 31 mbus data bus funky quadrature modulator i counter uv y cpu a ddress s pace a pertures protected mode aperture btv2115 brook t ree 109 bt the mbus address for each usin sample in 6 bit uv mode is generated as fol- lows: mbus_addr[21:2] = {guireg_mba[30:28], i_value[7:0], u_value[7:2], 3?000} where i_value[7:0] are the upper bits of the i counter shown in figure 10. the low- er bits of the i counter are supplied by a state machine as the 4 dwords are accessed. the u_value is supplied on the cpu data bus on the write u/v cycle; notice that in 6 bit uv mode, only bits 7:2 are used. in 8 bit uv mode, the address is as fol- lows: mbus_addr[21:2] = {guireg_mba[30], i_value[7:0], u_value[7:0], 3?000}. the mbus address for each vcos sample in 6 bit uv mode is generated as fol- lows: mbus_addr[21:2] = {guireg_mba[30:28], i_value[7:0], v_value[7:2], 3?100} the v_value is supplied on the cpu data bus on the write u/v cycle, notice that in 6 bit uv mode only bits 7:2 are used. in 8 bit uv mode the address is: mbus_addr[21:2] = {guireg_mba[30], i_value[7:0], v_value[7:0], 3?100} for all usin and vcos address the bottom 4 bits of the address, i.e. [3:0], are ef- fectively incremented as the 16 bytes of usin and 16 bytes of vcos data is fetched. table 68 shows that when writing composite plus and composite minus, 16 pix- els are sent per funky map write. table 67. write u/v ([22:21]=00) bits description 31:16 unused 15:8 v sample in 8 bit uv mode, 13:8 for 6 bit uv mode. 7:0 u sample in 8 bit uv mode, 13:8 for 6 bit uv mode. table 68. composite plus ([22:21]=01) bits description 31:24 y3 sample, causes fourth 32 bit write to frame buffer. 23:16 y2 sample, causes third 32 bit write to frame buffer. 15:8 y1 sample, causes second 32 bit write to frame buffer 7:0 y0 sample, causes ?st 32 bit write to frame buffer interpolated either from previous interpolation from the ?st y value on the line sent with the write composite index cpu cycle. cpu a ddress s pace a pertures protected mode aperture btv2115 brook t ree 110 bt the mbus address for each dword written as a result of the composite plus or composite minus write cycle is generated as follows: mbus_addr[21:2] = {guireg_mba[26],hbus_addr[20:2]} table 69 shows the bits of the write composite index. no vram cycles are performed in response to this operation. instead the i counter is initialized and the ?st y value for the line is put into the y interpolator. table 70 shows the bits of the composite minus ?ld. the difference between this cycle and that shown in table 68, ?omposite plus ([22:21]=01),?on page 109 is that the modulation performed is y?_value?_value instead of y+u_value+v_value. quadrature modulation of ntsc follows the following general sequence shown in table 71 for one 4:1:1 super pixel consisting of a u and v component and four y samples. this super pixel results in the writing of 16 pcm samples on each of two even lines and 16 pcm samples on each of two odd lines, for a total of 64 samples written to the media buffer. table 69. write composite index ([22:21]=10) bits description 31:24 reserved 23:16 composite index for sin/cos look up. 15:8 reserved 7:0 first y old value for interpolation on a line table 70. composite minus ([22:21]=11) bits description 31:24 y3 sample, causes fourth 32 bit write to frame buffer. 23:16 y2 sample, causes third 32 bit write to frame buffer. 15:8 y1 sample, causes second 32 bit write to frame buffer 7:0 y0 sample, causes 32 write to frame buffer cpu a ddress s pace a pertures protected mode aperture btv2115 brook t ree 111 bt table 71. quadrature modulator cpu bus example cycle type address data [31:24] data [23:16] data[15:8] data[7:0] comments writecomposite index and first y value any funky map addr w/ [22:21]=10 00h composite index reserved y n-1 written once per four lines of output write u/v any funky map addr w/ [22:21]=00 00h 00h vn un no write composite plus pcm w/ [22:21]=01 y n+3 y n+2 y n+1 y n write16 pcm sam- ples composite minus pcm w/ [22:21]=11 y n+3 y n+2 y n+1 y n write16 pcm sam- ples write u/v any funky map addr w/ [22:21]=00 0000h v n+1 u n+1 no write continue with next y samples cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 112 bt gui command/register map the command/data interface to the gui accelerator is mediated by a large queue which is implemented as an on-chip fifo (the gque) with an off-chip over?w fifo in vram (vque). the gque can hold up to 8 entries; the vque can be up to 64k entries in length. the vque is controlled by the guireg_fifo register and its start location and length in vram vary based on the driver. to prevent wrap-around and cor- ruption of data in the gque/vque, the driver must limit the addition of items to the queues. the depth of the queues is accessed in the gui_queue_depth ?ld of the guireg_depth register (see table 73). gui fifo register name: guireg_fifo address: gbase | 004000f8h, read/write size: 32 bit function: this register is accessed only via the non-queued interface and controls various aspects of the vque, including its location and size. table 72 shows the bit contents of the gui fifo register. upon reset, all bits are cleared. a write to this register will reset all gui queues to an initial empty state, except when bit [30] is set to allow masking. note the gui enable bit in con?uration register (grp_cfg4[0]) must be set before this register can be accessed. cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 113 bt table 72. gui fifo register (guireg_fifo) bit(s) name description 31 vfifo_enable 1 = enable vfifo. resets status bits in guireg_depth. 30 en_fifo_wr write-only. always reads back as zero. for diagnos- tics only. 1= enable a write only to gui_step and gui_freeze bits without affecting the other bits 0 = enable write to vfifo_base or vfifo_addr_mask. resets gque and vque to an initial empty condition. 29:28 unused must be zero 27:16 vfifo_base base address of vfifo. actual address interface as 8 zeroes appended to the lsb of the address to form an mbus address. 15 gui_freeze 1= stop sending commands from gque to the gui for diagnostic purposes. en_fifo_wr must be set. 0 = normal operation 14 gui_step 0->1 = step next command from gque to the gui into registers. must only be used when gui_freeze is a one. 13:6 reserved must be zero 5:0 vfifo_addr_ mask bits 5:0 mask bits 15:10 of all vfifo address calcu- lations. 0 means that the corresponding address is not modi?d as the vfifo address pointer is incre- mented. thus gui vfifos are allocated in powers of 2 dwords (starting at 256). a 6 bit mask value of 01h enables a 512 dword vfifo while a value of 0fh enables 4096 dword vfifos. vfifo start addresses are aligned on power of two boundaries at least as large as the vfifo size. dwords dwords 000000 - 256 00 1111 - 4k 000001 - 512 0 11111 - 8k 000011 - 1k 111111 - 16k 000111 - 2k cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 114 bt gui fifo depth register name: guireg_depth address: gbase | 004000f4h, read only size: 32 bit function: this register is only accessed via the non-queued interface. the pur- pose of this register is to provide information about the gui queues, such as the depth (total number of entries) in the gui queues (gque and vque) as well as giving software a way to determine whether the gui subsystem has completed all requested actions. table 73 shows the bit contents of the guireg_depth register. upon reset, all bits are cleared. note the gui enable bit in con?uration register (grp_cfg4[0]) must be set before this register can be accessed. table 73. gui fifo depth register (guireg_depth) bit(s) name description 31:24 unused reserved 23 gui_blt_ underflow 1=gui screen --> host blt under?w error 22 gque_ overflow 1=gui gque over?w error 21 gui_blt_ data_rqd 1=gui host --> screen write data required 20 gui_blt_ data_rdy 1=gui screen --> host read data ready 19 gui_busy 1=gui command processor busy 18 result_fifo_ busy 1=gui result fifo non-empty 17 gui_queue_ busy 1=gui queue processor busy 16 gui_fifo_ non_empty 1=gui gque fifo non-empty 15:0 gui_queue_ depth unsigned up-down counter used to track gui fifo depth of usage. depth counter = 0 for empty fifo. count increments for each word written to fifo; decrements for each word taken from fifo and sent to gui. this ?ld re?cts the combined total depth in both the gque and vque. cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 115 bt all gui commands, parameter values, and write data is queued either on-chip in the gque or off-chip in the vque. in addition, gui register values which can be queued will load their speci?d register ?n-order?with the gui com- mands. as shown in figure 11, there is an on-chip gque that gets consumed be- fore the over?w is written to vram so that if the gui accelerator is keeping up with its command arrival rate the vque will not be used and the vram band- width associated with the fifo will not be consumed. if the cpu attempts to ap- pend to the vfifo at the same time that the gui command processor attempts to retrieve from the vfifo, the cpu is granted access for the higher priority append operation. as shown in figure 12, the command/register map is divided into eight sub- maps of one mb each, numbered 0 through 7. each submap contains 16 blocks, each 64k long. submap 4 is a non-queued interface to the gui accelerator and be- gins at the gbase address plus 4mb. the queued interface map (submaps 3 figure 11. non-queued, queued and vram queued gui interface gque h ost b us i nterface h ost b us gui vram m edia b uffer pci/vl vram gui q ueue n on - queued i nterface gb ase + 4mb : gb ase + 5mb ?1 q ueued i nterface gb ase : gb ase + 4mb ?1 vque cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 116 bt through 0) begins at gbase+0mb. any command written to the queued interface will use the gque on the chip and may use the vque in vram. all commands to the non-queued interface will ?o-around?this fifo. all reads of any kind go around the fifo, thus driver software must insure that the gui accelerator state is consistent with a read operation by reading the guireg_depth to determine whether the gui is idle. figure 12. gui command/register map gbase gbase+4mb gbase+6mb gbase+7mb submap 7 submap 6 submap 5 submap 4 submap 3 submap 2 submap 1 submap 0 gbase+5mb flash rom yamaha fm synthesizer audio subsystem unused non-queued data non-queued registers queued commands (gui commands from table 94 on page 167) queued data queued registers (64k) (64k) (64k) (4m - 128k) (64k) (1m - 128k) (1m) (1m) (1m) gbase | 00000000h gbase | 0000ffffh gbase | 00010000h gbase | 0001ffffh gbase | 00020000h gbase | 003fffffh gbase | 00400000h gbase | 0040ffffh gbase | 00410000h gbase | 0041ffffh gbase | 00420000h gbase | 004fffffh gbase | 00500000h gbase | 005fffffh gbase | 00600000h gbase | 006fffffh gbase | 00700000h gbase | 007fffffh cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 117 bt below, table 74 indicates the read/write characteristics of the contents of the submaps. software can read the current depth of the gque/vque through the non- queued interface to effect ef?ient management of the gque/vque. the fifo is implemented with two address registers and an up/down counter. the address reg- isters implement a ring buffer, wrapping at a power of two boundary, as speci?d by driver initialization code. writing to guireg_fifo will clear the gque/vque, resetting the counter to zero and reloading the starting address for the vque. notice that each com- mand, register, or data packet in the gque/vque will contain a 32 bit address followed by zero or more 32 bit data values. the gque/vque implements a compression technique to reduce the unnec- essary storage of addresses in either the vram or on-chip fifos. this compres- sion stores the address ?ld of the ?st word of a command, however for subsequent parameter dwords no address is stored. similarly, for host to screen blts, the data length is stored in the ?st location in the fifo, subsequent data words are stored without inserting address values. for queued register writes, an address is stored for every register data word in the fifo. thus an n parameter command would occupy n+1 locations in the fifo. similarly, an m dword data transfer would store m+1 locations in the fifo. in calculating whether a command can be sent to the gui, one must make sure that there is at least n+1 locations re- maining in the fifo by checking the guireg_depth register. as reading the guireg_depth register is a time consuming proposition, one might keep track of the available space in a variable in the x86 memory. flash rom support submap 7 at gbase+7mb is used to access all of the flash ep rom residing on the vram data bus. in the btv2115, this can be up to 1mb of flash rom. the rom in this submap is used to hold the windows nt hardware abstraction layer. the vga bios rom is visible as the ?st 32 k of this flash rom space. flash rom can be read or written through the protected mode aperture. writing is only enabled when the appropriate con?uration register bit is also set. table 74. submap read/write characteristics submap region read write non-queued data used in screen-to-host blts ignored non-queued registers possible possible queued commands ignored possible queued data ignored used in host-to-screen blts queued registers ignored possible cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 118 bt below, figure 13 shows that up to one mb of flash rom can be accessed when the cpu address bits 31:25 match the gui_base register bits 31:25 (pm_base) and cpu address bits 24:20 equal 5?00111. cpu address bits 17:2 and the byte enables are passed out the vram data bus so that one mb is addressed for read or write. note flash rom can only be written after the unlock se- quence (see ?nlock register?on page 67) has been sent to it and must be written in ?ectors,?refer to the appropriate flash rom vendor s speci?ation. in addition, flash rom writes are inhibited by the de- fault state of con?uration register grp_cfg4 bit 6 (see ?on?uration registers?on page 47). cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 119 bt if we make the following c de?itions: #define pm_rom 0x00700000 // prot mode rom then location 300 in the rom can be accessed through the protected mode as fol- lows: ((unsigned char *) (gbase | pm_rom | 0x00000300l)) figure 13. flash rom access address mapping flash rom submap 0 1 2 19 24 : 20 31 . . . . . . 25 gui_base 0 31 cpu address hbus address/control 1m 2m 32m 0 1 2 21 . . . mbus address/control 1m 4m 0 0 1 1 1 gbase[31:25] 1 mb address 24 : 20 19 25 1 2 match protected mode accessed flipper straight 0 31 cpu data bus 0 31 mbus data bus 7 8 byte steering 24?xxxxxx 0 31 vram mdata bus 7 8 flash rom addr data cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 120 bt note that flash rom can also be accessed through the ?ga rom aperture on page 129. yamaha support in btv2115, the four bytes of yamaha opl3 register (or the eight bytes of opl4) are repeated continuously through the entire 1mb space of submap number 6. the legacy audio i / o space is mapped by the host bus interface into exactly the same hbus address range as the protected mode aperture uses when addressing this submap. figure 14 shows that the yamaha fm synthesizer can be accessed when the cpu address bits 31:25 match the gui_base register bits 31:25 (pm_base) and cpu address bits 24:20 equal 5?00110 cpu address bits 17:2 and the byte enables are passed out the vram data bus so that the eight bytes of opl4 regis- ters are addressed for read or write. if we make the following c de?itions: #define pm_yamaha 0x00600000 // prot mode yam then location 388 in the yamaha legacy audio i/o space can be accessed through the protected mode as follows: ((unsigned char *) (gbase | pm_yamaha | 0x00000388l)) note legacy audio supports the yamaha 2 and 4 operator mode fm synthesizer chip family, with direct support for opl3. cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 121 bt figure 14. yamaha access address mapping submap 0 1 2 19 24 : 20 31 . . . . . . 25 gui_base 0 31 cpu address hbus address/control 1m 2m 32m 0 1 2 21 . . . mbus address/control 1m 4m 0 0 1 1 0 gbase[31:25] 1 mb address 24 : 20 19 25 1 2 match protected mode accessed flipper straight 0 31 cpu data bus 0 31 mbus data bus 7 8 byte steering 24?xxxxxx 0 31 vram mdata bus 7 8 yamaha fm synthesizer addr data yamaha ? cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 122 bt audio subsystem the registers for the audio subsystem of the btv2115 are mapped into the 1mb of submap number 5, see figure 12. the audio subsystem provides a legacy audio pro compatible interface for use in the dos environment and an improved win- dows sound device driver support mode. the host bus interface maps the corre- sponding legacy audio i / o into an hbus address thus the actual legacy audio registers are accessible either as i / o registers or as memory mapped i / o in the pro- tected mode aperture. if we make the following c de?itions: #define pm_audio 0x00500000l // prot mode audio then location 100 in the audio subsystem can be accessed through the protected mode as follows: ((unsigned char *) (gbase | pm_audio | 0x00000100l)) for details on the audio subsystem, refer to the ?udio interface?chapter start- ing on page 271. figure 15. audio access address mapping submap 0 1 2 19 24 : 20 31 . . . . . . 25 gui_base 0 31 cpu address hbus address/control 1m 2m 32m 0 0 1 0 1 gbase[31:25] 1 mb address 24 : 20 19 25 1 2 match protected mode accessed 0 31 cpu data bus audio subsystem audio 0 31 hbus data bus cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 123 bt gui base address register name: grp_gui_base[3:0] index: 23h:20h, read/write size: 32 bit function: the gui base address register occupies four bytes of vga graphics register indexed space. these bytes are in the extension space of the vga, which means they are normally not accessible to vga pro- grams unless the extensions have been unlocked. once unlocked, the gui base address register is accessible at index 20h through 23h. the indices are loaded into the vga graphics index register at i / o address 03ceh. the register values are accessed through the vga graphics data register at i / o address 03cfh. the gui base address register is a 32 bit register with the least sig- ni?ant byte at index 20h and the most signi?ant byte at 23h so that: index 20h has gui base [07:00] index 21h has gui base [15:08] index 22h has gui base [23:16] index 23h has gui base [31:24] table 75 de?es the bit contents of the gui base address register for both 32k and 64k apertures. upon reset, all bits are cleared. cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 124 bt table 75. grp_gui_base address register (1 of 2) bits in 64k apert. bits in 32k apert. field description 31:25 31:25 pm_base these seven bits are used to match against the upper seven bits of all vl and pci memory addresses. the protected mode aper- ture is accessed when such a match occurs. in addition, no match will occur unless at least one of the pm_base bits is set to one. this insures that the protected mode aperture can not over- lay dos memory from 00000000h to 000fffffh (blocking access to the lower 32mb of the cpu memory address space). thus software cannot inadvertently cause a collision between system memory and the protected mode aperture. the protected mode aperture is disabled when this register is set to zero. 24 24 pm_enable this bit must be set to one to enable the protected mode aper- ture. this bit controls whether the entire 32mb aperture is acces- sible. 23 23 reserved 22 22 enable_a0000 1 = ignore graphics miscellaneous register memory map = 01 in the a0000 to affff range and force the decoder to accept cpu read/write cycles. (see table 14 on page 42.) 0 = graphics miscellaneous register controls a0000 to affff. 21 21 ? 32k_apertures 1= 32k real mode aperture 0= 64k real mode aperture cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 125 bt mba control register name: guireg_mba address: gbase | 004000f0h, read/write size: 32 bit function: the media buffer aperture ( mba) control register controls various functions of the mba, like flippin map ?p controls, funky map com- ponent access versus quadrature modulation modes, etc. and holds the vram pointer to the quadrature modulator sin/cos table. there are in- dependent ?p controls for funky map, flippin map and most every- thing else, but there is no way to ?p the direct map, rom reads/ writes, and accesses to the yamaha and audio subsections. table 76 de- ?es the bit contents of the gui mba register. upon reset, all bits are cleared. __ 20 ? enable_32k_ apertures if bit 21 =1 and bit 20 = 1: enable 32k real mode apertures 20:19 ___ unused if bit 21=0 then these are unused 18 ___ ? enable_64k_ real if bit 21=0 and bit 18 = 1: enable 64k real mode apertures 17:9 19:10 ? real_mode_ aperture1 these bits are appended as the high order address bits of a 25 bit address which is applied to the hbus as if it had come from a protected mode reference to gui_base. the lower 16 bits for 64k mode or 15 bits for 32k mode come from the memory address of a read or write to a location determined as follows. 64k mode: 000b0000h - 000bffffh 32k mode: 000a8000h - 000affffh 8:0 9:0 ? real_mode_ aperture0 these bits appended as the high order address bits of a 25 bit address which is applied to the hbus as if it had come from a protected mode reference to gui_base. the lower 16 bits for 64k mode or 15 bits for 32k mode come from the memory address of a read or write to location determined as follows. 64k mode: 000a0000h -000affffh 32k mode: 000a0000h - 000a7fffh ? to set 32k mode, bits 20 and 21 must be 1 to set 64k mode, bit 18 must be 1 and bit 21 must be 0 (refer to ?eal mode aperture?on page 127 for more information.) note the gui enable bit in con?uration register (grp_cfg4 [0]) must be set before this register can be accessed. table 75. grp_gui_base address register (2 of 2) bits in 64k apert. bits in 32k apert. field description cpu a ddress s pace a pertures gui command/register map btv2115 brook t ree 126 bt table 76. gui mba control register bits field description 31:28 sincos_addr sin/cos table pointer upper four bits of an 8mb mbus memory address. only three bits are used in the btv2115. 27:26 modul_base modulation output base address 00 = sev frame buffer is in ?st 2mb of media buffer. 01 = sev frame buffer is in second 2mb of media buffer. 10 = sev frame buffer is in third 2mb of media buffer. 11 = sev frame buffer is in fourth 2mb of media buffer. 25 uv_6bit 6-bit/8-bit uv values for modulation 1 = u and v values are most signi?ant 6 of the supplied 8 bits. 0 = all eight bits of u and v are used 24 ycrb_422mode 4:2:2/4:1:1 mode for ycrcb 1 = 4:2:2 format 0 = 4:1:1 format 23 modul_en enable modulation logic 1 = funky map con?ured to perform quadra- ture modulation for sev. 0 = funky map con?ured to perform compo- nent access for read and write. 22 reserved must be 0 21 flippin_word flippin map word ?p control, 1=?p 20 flippin_byte flippin map byte ?p control, 1=?p 19 flippin_bit flippin map bit ?p control, 1=?p 18 reserved must be 0 17 cmd_word command map word ?p control, 1=?p 16 cmd_byte command map byte ?p control, 1=?p 15 cmd_bit command map bit ?p control, 1=?p 14 reserved must be 0 13 funky_word funky map word ?p control, 1=?p 12 funky_byte funky map byte ?p control, 1=?p 11 funky_bit funky map bit ?p control, 1=?p 10:4 yamaha_delay yamaha delay in mclks, default = 16 mclks 3:0 reserved must be 0 cpu a ddress s pace a pertures real mode aperture btv2115 brook t ree 127 bt real mode aperture the vga aperture mechanism allows access to the 32mb protected mode aper- ture from 486 real mode. this mechanism involves changing the interpretation of the vga memory aperture at 000a0000h-000bffffh so that it provides access to the various hbus agents instead of to the vga frame buffer. two vga apertures are provided to offer the most robust support of the vesa bios modes. for 64k mode, two 64kb apertures are available for accessing different hbus agents or for accessing different places within a single hbus agent. this access of hbus agents is enabled when gui_base[ 18] is set to one and gui_base[21] is set to zero. real_mode_aperture0 responds to cpu reads/writes in the address range 000a0000h through 000affffh. the hbus is accessed by a 25 bit address; gui_base[8:0] (real_mode_aperture0) de?es the upper 9 bits and cpu address [15:0] de?es the lower 16 bits to form the hbus address as fol- lows: hbus_addr[24:0]={gui_base[8:0],cpu_address[15:0]} the resulting address is fed to the hbus decoder as if it had come through the protected mode aperture. thus when gui_base [8:0] is loaded with 071h and when the cpu accesses vga_aperture0, then cpu reads/writes to address range 000a0000h - 000affffh will access the hbus agent (flash rom) at rom locations 10000 through 1ffff, i. e. the second 64k byte block (refer to figure 12 on page 116). 64k mode real_mode_aperture1 responds to cpu reads/writes in the address range 000b0000h through 000bffffh. the hbus is accessed by a 25 bit address; gui_base[17:9] (real_mode_aperture1) de?es the upper 9 bits and cpu address [15:0] de?es the lower 16 bits to form the hbus address as follows: hbus_addr[24:0]={gui_base[17:9],cpu_address[15:0]} this mechanism is useful for accessing all parts of btv2115 when the cpu is running in real mode, as occurs at power on. in 32k mode, access of hbus agents is enabled when gui_base[ 20] and gui_base[ 21] are set to one. real_mode_aperture0 responds to cpu reads/writes in the address range 000a0000h and 000a7fffh. the hbus is ac- cessed by a 25 bit address; gui_base[9:0] (real_mode_aperture0) de- note cpu address[1:0] is actually expressed via byte en- ables. cpu a ddress s pace a pertures real mode aperture btv2115 brook t ree 128 bt ?es the upper 10 bits and cpu address [14:0] de?es the lower 15 bits to form the hbus address as follows: hbus_addr[24:0]={gui_base[9:0],cpu_address[14:0]} 32k mode real_mode_aperture1 responds to cpu reads/writes in the address range 00a7fffh through 000affffh. the hbus is accessed by a 25 bit address; gui_base[19:10] (real_mode_aperture1) de?es the upper 10 bits and cpu address [14:0] de?es the lower 15 bits to form the hbus address as follows: {gui_base[19:10],cpu_address[14:0]} the vga aperture mechanism has many applications. for example, it is useful for bios routines that want to read more rom data than is available in the vga video bios space from c0000 to cffff, since setting the vga_aperture register to 070h sets the mba address to submap 7, i.e. the flash p rom space. setting the vga_ aperture register to 050h makes the audio registers avail- able from real mode 80486 code. when enable _vga_crtc is set (grp_cfg4[2]), memory references to the vga aperture are redirected to an hbus agent. cpu a ddress s pace a pertures vga rom aperture btv2115 brook t ree 129 bt vga rom aperture the vga rom aperture runs from 000c0000h to 000c7fffh. it can be selec- tively disabled by a bios enable con?uration bit (grp_cfg4[5], refer to table 22 on page 50) when btv2115 is mounted on the motherboard and the sys- tem rom is used to hold video rom code. even when the vga rom aperture is enabled, a section from c6000 to c67ff can be disabled. when the vga rom aperture is enabled, hbus addresses are formed by concatenating the cpu ad- dress bits [14:2] with grp_rompage[5:0] and pre-pending ?0111?to the top to access the flash rom: hbus_addr[24:2]={[5?00111,grp_rompage[5:0],cpu_addr[14:2]} thus any 32k page of the possible 1mb flash rom can be mapped into the vga rom aperture. the vga rom aperture is not available on pci base systems. instead, a pci compliant expansion rom address register under the control of the pci system bios is used to map the 1mb rom space. when the vga rom aperture is en- abled, hbus addresses are formed by concatenating the cpu address bits [19:2] with ?0111?to access the flash rom: {[5?00111,cpu_addr[19:2]} for further information, refer to ?ci con?uration space?on page 219. cpu a ddress s pace a pertures cpu apertures in a pci-bus environment btv2115 brook t ree 130 bt cpu apertures in a pci-bus environment pm_base field the pm_base ?ld of the gui_base register is also read and written in a pci- bus environment whenever pci con?uration registers are accessed for the btv2115. speci?ally, whenever pci_base0_reg is accessed for pci function 0. for further detail, refer to ?ci base address registers?on page 222. when pci system bios writes all ones to pci_base0_reg then only the bits in pm_base respond, telling the bios that a 32mb aperture is available. the bios next loads pci_base0_reg with the address assignment for the btv2115 protected mode aperture. pci_base0_reg is ?gged non-prefetchable so the pci system bios knows to mark this aperture as non-prefetchable in the pci bridge. this aperture is marked because the audio/yamaha and gui submaps have read side effects. prefetch base because a non-prefetchable aperture status in an intelligent pci bridge can cost signi?ant performance, the btv2115 offers a second and independent 32mb ap- erture when in pci mode. this aperture is the prefetchable aperture and when en- abled is accessed via the pci_prefetch_base pci con?uration register. this register is marked prefetchable and will be assigned to a separate and non-overlap- ping 32mb address range in the cpu address space. from an address decode per- spective, the btv2115 treats this 32mb aperture as an alias of the protected mode aperture found through pm_base. one can safely access the direct, flippin and funky maps as well as the rom submap through the prefetchable aperture. one should never access anything in the ?st 7mb of the prefetchable aperture. because the rom can be safely access- ed through either map it serves as the neutral zone between safe and unsafe. soft- ware should restrict rom accesses to the protected mode aperture so that an intelligent bridge will not attempt to opportunistically read ahead into the yamaha submap. cpu a ddress s pace a pertures cpu apertures in a pci-bus environment btv2115 brook t ree 131 bt pci constraints on gbase because of the plug? play nature of the pci, the protected mode aperture address value can not be speci?d as a constant for any software that will run in a pci en- vironment. the de?ition of gbase, above, was intentionally over simpli?d as a c preprocessor constant. in actuality it must be a program variable, loaded at ini- tialization time from the pm_base ?ld of the gui_base register. in addition, the possible existence of a prefetchable aperture means the two ad- dress pointer variables must be de?ed and utilized. any software touching the di- rect, flippin or funky maps should use the second variable. at initialization, software should look at grp_cfg[7] bit 7, which if set, indicates that the second aperture is operational and should be used if pci system bios enabled it. if the prefetchable base is turned off, then both address pointers should be loaded from pm_base. to review, the prefetch aperture could have been turned off by a con- ?uration strap, by the pci bios being unable to assign a 32mb address range to it, or by virtue of the btv2115 being installed in a vl environment. brook t ree 133 bt c onfiguration r egisters introduction the btv2115 mediastream controller provides a set of registers for specifying operating parameters for interaction of the multimedia subsystem components (both internal and external to the btv2115). the con?uration registers consist of eight bytes controllable by software within the vga graphics controller exten- sion registers, writing values 40h-47h to the index/address register (03ceh) and reading or writing data at the data register location (03cfh). address 40h corre- sponds to grp_cfg0, address 41h corresponds to grp_cfg1, etc. for details on the bit contents of the eight con?uration registers, refer to ?on- ?uration registers?on page 47 of the ?egister de?itions?chapter. c onfiguration r egisters register initialization btv2115 brook t ree 134 bt register initialization at reset all bits contained in the con?uration registers are initialized. those bits which have reset values de?able by the user are initialized based on logic levels present on mdata pins. not all bits of the mdata bus are used, but those that are used can be programmed by strapping the pin to either vdd or vss. pin strap- pings should utilize a high value resistor (20k-ohms is recommended) to tie the pin to either vdd or vss, as shown in figure 16. figure 17 shows the pins of the mdata bus which affect the initialization state of the con?uration registers. note that pins mdata[15:6] directly affect the ini- tialization of vram_type ?ld. the value applied to mdata[15:6] appears in grp_cfg7 and grp_cfg0. these con?uration registers contain vram -spe- ci? parameters which are initialized at reset to their expected values by loading their values from mdata[15:6]. the bits contained in grp_cfg0 may be cus- tomized by the user after reset by simply overwriting the initial value as needed. the value in grp_cfg7[5:0] indicates the memory con?uration of the system and therefore is read-only. figure 16. con?uration resistor straps mdata[25:6] vram vdd vss 20k = 0 20k = 1 tie high or low through 20k ohms. 4 2 6 mdata[31:26] ?44 monitor_id[27:26] monitor_id[31:28] btv2115 c onfiguration r egisters register initialization btv2115 brook t ree 135 bt the chip_model_code bits are also read-only since they re?ct the func- tional capability built into the btv2115. note that chip_model_code[0], which re?cts the availability of a pci bus interface, is not directly readable by the program. furthermore, notice that the bus type is read-only. the bus type is pro- grammed by con?uration strap resistors according to which bus type the btv2115 is attached, as follows: the mapping between chip model code bits and btv2115 part numbers is given in table 78. notice that the /v versus /p coding cannot be determined program- matically. if a chip s con?uration registers can be successfully read via pci cy- cles, then it is a /p version of the btv2115. if a chip s con?uration registers can be successfully read by a vl bus cycle, it can be either a /v or /p part number. chip_model_code[3] indicates whether the vram gui queue is present in the btv2115. the monitor_id bits [31:26] are also sampled at reset, indicating the type of monitor connected. monitor_id bits [31:28] are pulled-up and bits [27:26] are pulled-down but not used. as shown in figure 16, a design providing monitor id bits would use a ?44 to gate these bits onto mdata bits [31:26] during reset. table 77. bus type encode mdata [18:17] con? reg 3 bits 4:3 bus type vss: vss 0: 0 vesa local bus vss: vdd 0: 1 pci 32 vdd: vss 1: 0 reserved vdd: vdd 1: 1 reserved table 78. chip model coding chip_model_code [2:1] part # for chip_ model_code [0]=0 part # for chip_ model_code [0] = 1 00 reserved reserved 01 reserved reserved 10 reserved reserved 11 btv2115/v btv2115/p c onfiguration r egisters register initialization btv2115 brook t ree 136 bt figure 17. con?uration registers and strapping bits for btv2115 0 2mbit_refresh disable_refresh block_mode[1] ram_speed[0] vga_sync_sel 6 5 3 1 7 4 2 0 c f g 0 6 5 3 1 7 4 2 0 c f g 1 block_mode[0] rom_speed audio c f g 3 decode_test rom_hole_enable fast_gui dual_cas enable_gui enable_pacdac enable_vga_crtc bios_enable snoop_dac 6 5 3 1 7 4 2 0 c f g 4 adapter_sleep_sel clk_mod_reset sam_length 7 0 c f g 2 refresh_rate[0] refresh_rate[7] bios_enable 6 5 3 1 7 4 2 0 decode_test rom_hole_enable adapter_sleep_sel 14 13 11 9 15 12 10 8 rom_speed 22 21 19 17 23 20 18 16 mdata[31:0] configuration registers grp_cfg[7:0] enable_vga_crtc_gen monitor_id[0] 6 5 7 0 c f g 5 rom_wrt_enable monitor_id[5] 0 0 16 19 21 20 22 0 0 0 0 0 0 0 0 default value vram_type[3] vram_type[0] vram_type[1] vram_type[2] 0 vram_type[4] vram_type[5] 2 4 4 from crt chip_model_code[3:1] video bus_type_lo ram_speed[1] 6 5 3 1 7 4 2 0 wakeup_state pci_prefetch_base c f g 6 vram_type[0] 6 5 7 0 vram_type[5] 25 monitor_id[0] 25 26 31 24 monitor_id[5] c f g 7 note 1: the terms used in this ?ure to describe the con?uration register bits for grp_cfg[7:0] are descriptive only - they are not addressable names. read only read only ... ... ... bus_type_hi wakeup_state chip_model_code[0] bus_hi bus_lo 24 note 2: vram_type to con?uration regis- ter mapping is given in table 139, ?up- ported vram types,?on page 229 1 6 5 3 1 7 4 2 0 pci_en_burst pci_2ckwr pci_1cyc_rdsync irq_polarity aud_clk select 1 0 1 23 aud_100x 1 0 1 pci_prefetch_base enable_save_restore burst_req_size4 block_wrt_enable ... bios_reset_state spare b spare a 0 0 0 comm_dcd_enb comm_base_hi comm_base_lo mpu_dcd_enb joy_dcd_enb 0 0 0 0 0 0 dual cas 2mbit refresh 0 spare b spare a . . . . . b4 brook t ree 137 bt i 2 c m aster and s lave c ontrollers introduction this chapter speci?s the programming interface to both the i 2 c master and i 2 c slave modules of the btv2115 media controller. both of these blocks operate in- dependently of each other so they are documented separately. the btv2115 supports two independent i 2 c buses, referred to here as iic and iic_ddc. both support access.bus protocols. iic_ddc has additional logic to support vesa monitor ddc1, ddc2, and ddc2b signalling. since there is only one master controller and one slave controller, only one i 2 c bus can be designated as the access.bus. typically if a ddc2b monitor is detected, it will provide fanout of the access.bus. the i 2 c block consists of the i 2 c master module, the i 2 c slave module and a small amount of shared logic. the i 2 c master module is capable of transmitting and receiving data over the i 2 c bus as an i 2 c bus master. this functionality is re- quired for the i 2 c links to the btv2487 and btv2811a chips and is also required to support the access.bus protocol which is built on top of the i 2 c protocol. the i 2 c slave module is capable of receiving data over the i 2 c bus as an i 2 c bus slave. this functionality is not required for the i 2 c links to btv2487 and btv2811a; it is required solely to support the access.bus protocol. two sets of i 2 c pins allow the btv2115 to support the iic and iic_ddc bus- ses. this means that the btv2487 and btv2811a i 2 c bus can be isolated from the access.bus bus. the i 2 c master and slave modules can be independently switched from one bus to the other. the switching of the master and slaves mod- ules to the iic and iic_ddc busses is controlled by the grp_i2c_ctrl(r/w) control register, which is de?ed in the next subsection. the i 2 c master module is capable of transmitting and receiving data over the i 2 c bus and is controlled through two vga extension registers. both master trans- mit and master receive modes are required by the btv2115 to btv2487 i 2 c com- munication link. this module ful?ls all these requirements. support for the access.bus spec requires the master transmit and slave receive modes, however this module does not provide the slave receive mode; this must be ful?led by the i 2 c slave module. the i 2 c slave module is capable of receiving data over the i 2 c bus as a slave de- vice and is controlled through two vga extension registers. i 2 c m aster and s lave c ontrollers i 2 ccontrol register btv2115 brook t ree 138 bt this controller is designed to work either polled or interrupt driven in an oper- ating environment that has many other interrupts being serviced for other devices. for example, if a clock interrupt occurs in the middle of an i 2 c receive using a polling design, no i 2 c data will be lost. this module is designed to implement the operations of an i 2 c and ac- cess.bus interface with the assistance of system software . it is possible for the system software to make this hardware perform in violation of either the i 2 c or access.bus specs. this design assumes that the system software does not at- tempt to do any such illegal activities and the design makes no attempt to protect against this eventuality. i 2 c control write register name: grp_i2c_ctrlw index: 4bh, write size: 8 bit function: this register enables the i 2 c serial control interface. the bit contents of the grp_i2c_ctrlw control register are shown in table 79. note the i 2 c interrupts are de?ed in table 165, ?nterrupt status, state and mask register bits,?on page 291. for electrical speci?ation and timing for i 2 c i/o stag- es and bus lines, refer to the philips semiconductor publication the i 2 c-bus and how to use it . table 79. grp_i2c_ctrlw control register (1 of 2) bit function detail 7 i2cma_sel 1 = select iic bus for master module 0 = select iic_ddc bus for master module 6 i2csl_sel 1 = select iic bus for slave module 0 = select iic_ddc bus for slave module 5:4 reserved set to zero. i 2 c m aster and s lave c ontrollers i 2 ccontrol register btv2115 brook t ree 139 bt as shown in the above table, bits grp_i2c_ctrlw[3:0] allow the override the output levels of the scl clock and sda data pins for both i 2 c busses. these overrides could be used to freeze one i 2 c bus while another is busy; for example, temporarily switch the i 2 c master module to the other bus for a transmit/receive. or, these bits could be used to implement an i 2 c interface purely in software (a cpu-intensive task). loopback occurs when the master and slave are both switched to the same iic or iic_ddc bus. under the control of software, the master can receive data trans- mitted by the slave; and the slave can receive data transmitted by the master. i 2 c control read register name: grp_i2c_ctrlr index: 4bh, read only size: 8 bit function: this register enables the i 2 c serial control interface. the bit contents of the grp_i2c_ctrlr control register are shown in figure 79. 3 ovr_iic_scl override scl clock signal in iic bus 1= release scl clock 0= force scl clock low 2 ovr_iic_sda override sda data pins in iic bus 1= release sda data 0= force sda data low 1 ovr_ddc_scl override scl clock signal in iic_ddc bus 1= release scl clock 0= force scl clock low 0 ovr_ddc_sda override sda data pins in iic_ddc bus 1= release sda data 0= force sda data low table 80. grp_i2c_ctrlr control register (1 of 2) bit function detail 7 i2cma_sel 1 = select iic bus for master module 0 = select iic_ddc bus for master module 6 i2csl_sel 1 = select iic bus for slave module 0 = select iic_ddc bus for slave module 5 i2cma_done i 2 c master module done. read-only value from grp_i2c_mctrlr 4 i2csl_done i 2 c slave module done. read-only value from grp_i2c_sctrlr table 79. grp_i2c_ctrlw control register (2 of 2) bit function detail i 2 c m aster and s lave c ontrollers i 2 ccontrol register btv2115 brook t ree 140 bt as shown in the above table, bits grp_i2c_ctrlr[3:0] provide for reading the pin values of the four i 2 c pins. these bits could be used to implement an i 2 c interface purely in software (a cpu-intensive task). these bits also provide sup- port for vesa monitor ddc1 signalling. 3 rd_ iic_scl read scl clock signal in iic bus (read only) 2 rd_ iic_sda read sda data pins in iic bus (read only) 1 rd_ ddc_scl read scl clock signal in iic_ddc bus (read only) 0 rd_ ddc_sda read sda data pins in iic_ddc bus (read only) table 80. grp_i2c_ctrlr control register (2 of 2) bit function detail i 2 c m aster and s lave c ontrollers i 2 cmaster module software interface btv2115 brook t ree 141 bt i 2 c master module software interface the software interface to the i 2 c master block is via two vga graphics extension registers: grp_i2c_mctrl (index 4eh) and grp_i2c_mdata (index 4fh). both of these registers behave differently when read and written so the interface actually consists of two write-only registers and two read-only registers. in general it is necessary to access both the grp_i2c_mctrl and grp_i2c_mdata registers at least once per byte of data transmitted / received. the order of reading the grp_i2c_mctrl and grp_i2c_mdata registers is important. the data received in the grp_i2c_mdata register should not be con- sidered valid until after the done bit has been read as ??in the grp_i2c_mctrlr register. similarly the tran or recv bits in the grp_i2c_mctrlw register (start to transmit / receive data) should not be writ- ten ??until after the relevant data has been read from or written to the grp_i2c_mdata register. note that the i 2 c master module detects but does not recover from arbitration loss, non-acknowledgment of data, etc. it is the responsibility of the system soft- ware to handle any problems like this that occur and resubmit any failed action to the i 2 c master module. the software interface to the i 2 c master module is via the following registers. i 2 c master data register name: grp_i2c_mdata index: 4fh, read/write size: 8 bit function: this register supplies the contents of the input data buffer containing data received over the i 2 c bus. the bit contents of the grp_i2c_mdata register are shown in table 81. if this register is read while data reception is still in progress the data read will be incorrect (not all bits will be shifted in yet). it is the responsibility of the system software to wait until the data reception on the i 2 c bus is complete before it con- siders the data read from the grp_i2c_mdata register to be correct. this can be done by examining the done bit in the grp_i2c_mctrlr register and waiting until it is ?. when written, the grp_i2c_mdata register supplies the data to be transmit- ted over the i 2 c bus. if this register is written while data transmission is still in progress the data transmitted will be incorrect. it is the responsibility of the system table 81. i 2 c master receive data grp_i2c_mdata bit function detail 7:0 data received data byte/ data byte to transmit i 2 c m aster and s lave c ontrollers i 2 cmaster module software interface btv2115 brook t ree 142 bt software to wait until the data transmission on the i 2 c bus is complete before it at- tempts to write to the grp_i2c_mdata register. this can be done by examining the done bit in the grp_i2c_mctrlr register and waiting until it is ??before writing to the grp_i2c_mdata register. please note that the registers used for data reads and writes are the same, writing data to the grp_i2c_mdata register will overwrite any unread data from the previous i 2 c master module reception. similarly, any data written to the grp_i2c_mdata register could be corrupted by an i 2 c receive operation. also, if two consecutive i 2 c transmit operations are performed with the same data, you still need to rewrite the required data to the grp_i2c_mdata register between the two i 2 c transmissions in order to remain compatible with future hardware re- visions. finally, note that upon reset the initialization of the contents of this register is not de?ed. assume that after a reset this register contains junk data until data has been written to it by the system software or until data has been loaded into it by an i 2 c master module receive operation. i 2 c master control read register name: grp_i2c_mctrlr index: 4eh, read only size: 8 bit function: this register supplies status information about the progress / comple- tion of any i 2 c bus transaction. the bit contents of the grp_i2c_mctrlr registers are shown in table 82. grp_i2c_mctrlr[7] the done bit is set to ??whenever the i 2 c master module has ?ished its cur- rent operation and is ready for another request from the system software. it is set to ??whenever the i 2 c master module is busy servicing a request. this bit can be used by the system software to determine whether the i 2 c master module was the source of an interrupt (interrupts enabled) or to check whether the i 2 c master ?- ished the current request (software polling, interrupts disabled). this bit is used in the generation of the i 2 c interrupt (it is anded with the inte interrupt enable bit table 82. i 2 c master read control register grp_i2c_mctrlr bit function detail 7 done 0 = i 2 c master module busy 1 = i 2 c master module ?ished current operation 6 lost 0 = arbitration not lost 1 = arbitration lost 5 rack value of last i 2 c acknowledge bit received 4 mast 0 = i 2 c master module not bus master 1 = i 2 c master module is bus master 3:0 bits number of bits processed. see table 83 i 2 c m aster and s lave c ontrollers i 2 cmaster module software interface btv2115 brook t ree 143 bt together with any outstanding requests in the grp_i2c_mctrlw register) but it is set independently of the value of inte (interrupt enable). it is set only when all of the request bits (tsta, tran, recv and tsto) in the grp_i2c_mctrlw register are cleared. the done bit is set under the following conditions. tsta = 1: (start request) the done bit is set after the start token is transmitted. tran = 1: (transmission request) the done bit is set after the data is transmitted and the acknowledge bit is received. recv = 1: (receive request) the done bit is set after the data is re- ceived and the acknowledge bit is transmitted. note that it is impossible to choose the value of the acknowledge bit dynamically based on the data received . tsto = 1: (stop request) the done bit is set after the stop token is transmitted onto the i 2 c bus. lost = 1: (arbitration lost) the done bit is also set whenever the i 2 c bus arbitration is lost. this will clear any outstanding requests in the grp_i2c_mctrlw register, i.e. losing bus arbitration clears the ts- ta, tran, recv and tsto bits. grp_i2c_mctrlr[6] (lost) arbitration lost. if the previous action was an i 2 c transmit, the lost bit is set when the i 2 c master module loses the arbitration process. the i 2 c arbitration pro- cess can also be lost during a receive action if the master module tries to send a ? acknowledge and another contending master tries to send a ??acknowledge. it is also possible to lose arbitration during the transmission of a stop token onto the i 2 c bus. grp_i2c_mctrlr[5] (rack) receive acknowledge. the rack bit contains the value of the acknowledge bit received or transmitted during the last transmit / receive. grp_i2c_mctrlr[4] ( mast) master bus. the mast bit indicates whether the i 2 c master module is actually the current i 2 c bus master (1=master). once this module becomes bus master it will remain so until either the system software tells it to release ownership by writing a ??to the tsto ?ld of the grp_i2c_mctrlw register or until it releases ownership due to an arbitration loss. grp_i2c_mctrlr[3:0] (bits) number of bits processed. the bits value indicates the number of the bit current- ly being processed, as shown in table 83. do not assume that an i 2 c transaction is ?ished until this ?ld has the value of 9 (?001?. however, the correct way to de- tect the completion of an i 2 c transaction is when the done status bit = 1. this ?ld is actually the contents of an internal counter within the i 2 c master module that counts the number of bits transmitted / received. thus, in the case of arbitra- tion loss it will indicate at which bit the arbitration was lost. i 2 c m aster and s lave c ontrollers i 2 cmaster module software interface btv2115 brook t ree 144 bt below, table 84 shows an example of possible settings of the grp_i2c_mctrlr bits. i 2 c master control write register name: grp_i2c_mctrlw index: 4eh, write only size: 8 bit function: the grp_i2c_mctrlw register controls the operation of the i 2 c master module. writing to this register initializes the done and bits ?lds in the grp_i2c_mctrlr register. initializing the bits ?ld in the grp_i2c_mctrlr register would destroy any i 2 c bus transac- tion in progress, so do not write to the grp_i2c_mctrlw register while the i 2 c master module is busy transmitting or receiving on the i 2 c bus. it is the responsibility of the system software to ensure that this reg- ister is never written to except when the i 2 c master module is idle (in- table 83. grp_i2c_mctrlr current bit bits[3:0] value meaning 0000 0 1 st bit in progress 0001 1 2 nd bit in progress ... ... ..... 0110 6 7 th bit in progress 0111 7 8 th bit in progress 1000 8 ack bit in progress 1001 9 all bits done table 84. example of reading grp_i2c_mctrlr register done lost rack mast bits description 1 0 x 0 x x x x idle, not bus master 0 0 x 1 0 1 0 0 currently bus master transmit/receive in progress 3 bits done. 00111 0 0 1 currently bus master transmit/receive done if receive, ack was 1. 0 0 x 0 0 0 0 0 transmit/receive in progress. no bits done, not bus master, but waiting for bus mastership. 1 1 x 0 0 0 0 1 not bus master lost arbitration on bit 2 of last transmit. i 2 c m aster and s lave c ontrollers i 2 cmaster module software interface btv2115 brook t ree 145 bt dicated by mast = 0 or bits = 1001 in the grp_i2c_mctrlr register). all the bits in this register except for tack are all set to ??upon reset. this reset initialization places the i 2 c master module in an idle state immediately after reset. a tack value of ??indicates a not-ac- knowledged state. the bit contents of the grp_i2c_mctrlw register are shown in table 85. grp_i2c_mctrlw[7] this bit is currently unused in the i 2 c master module, however the system soft- ware must always write ??here to allow for possible future expansions. rp_i2c_mctrlw[6] (400k) 400khz mode. when set to ?,?the 400k control bit causes the i 2 c master module to transmit at the full speed 400khz clock rate. when set to ?,?it uses a more con- servative 100khz clock rate (actually the rate is only 80khz but the timings are set up to satisfy the i 2 c 100khz mode spec). grp_i2c_mctrlw[5] (tsto) transmit a stop. when set to ?,?the tsto control bit causes the i 2 c master mod- ule to transmit a stop token onto the i 2 c bus. if this i 2 c master module is not bus master, then this control bit will be ignored. note that unlike tsta and tran, it is not possible to combine tsto with tran or recv. a separate command ac- cess by the system software is required to transmit a stop to the i 2 c bus. thus if tran, recv, or tsta are set to ??then tsto must be ?. table 85. i2c master write control register grp_i2c_mctrlw bit function detail 7 unused must write 0 here 6 400k 0 = 100khz mode 1 = 400khz mode ? 5 tsto 0 = not transmit a stop 1 = transmit a stop ? 4 tsta 0 = not transmit a start 1 = transmit a start 3 inte 0 = disable interrupts (software polling) 1 = interrupt enable 2 tack value of last i 2 c acknowledge bit received ? 1 recv 0 = no receive data 1 = receive data ? 0 tran 0 = no transmit data 1 = transmit data ? valid until the action requested is finished, then automatically reset i 2 c m aster and s lave c ontrollers i 2 cmaster module software interface btv2115 brook t ree 146 bt grp_i2c_mctrlw[4] (tsta) transmit a start. when set to ??the tsta control bit causes the i 2 c master mod- ule to transmit a start token onto the i 2 c bus. if the bus is busy, it will wait for the bus to become free before transmitting the start token. if this i 2 c master module is already bus master, it will transmit the start token immediately. if the tran con- trol bit is also set to ?,?the i 2 c master will transmit the contents of the grp_i2c_m data register immediately after the start token. the combination where both the tsta and tsto bits are written as ??is illegal and the operation of the i 2 c master module is not de?ed. grp_i2c_mctrlw[3] (inte) interrupt enable. when set to ?,?the inte control bit causes the interrupt output from the i 2 c master module to go to ??whenever the contents of the done ?ld goes to ??(i.e. at the end of a transmit or receive or arbitration loss). if this bit is set to ?,?the system software must service the i 2 c bus by means of software poll- ing. this action will not result in the loss of any data but may cause the i 2 c bus stand idle until the system software next polls this module and sets up the next re- quest. the actual interrupt is generated by anding this bit with the done bit of the grp_i2c_mctrlr read register. grp_i2c_mctrlw[2] (tack) acknowledge to transmit. the tack bit contains the value that the i 2 c master module will transmit whenever it needs to transmit an acknowledge bit. (i.e. when- ever it needs to acknowledge a i 2 c reception.) grp_i2c_mctrlw[1] (recv) receive data. when set to ?,?the recv bit will start the process of receiving the contents of the grp_i2c_mdata register from the i2c bus. note that the i2c master module must already be bus master (mast = 1 in the grp_i2c_mctrlr register). note also that since the i2c spec does not allow any circumstance where the i2c master follows a start with anything other than a transmit, this module does not support combining the action of the tsta bit with the recv bit as it does with tsta and tran to enable both a start and transmit. the combination where both the recv and tsta bits are written as ??is illegal and the operation of the i2c master module is not de?ed if this happens. grp_i2c_mctrlw[0] (tran) transmit data. when set to ?,?the tran bit will start the process of transmitting the contents of the grp_i2c_mdata register onto the i2c bus. note that the i2c master module must already be bus master (mast = 1 in the grp_i2c_mctrlr register) or the system software must write a ??to the tsta bit at the same time to initiate bus mastership. note also that the situation where both this bit and the recv bit are written as ??is illegal and will produce some unde?ed action in the i2c master module. below, table 86 shows an example of possible settings of the grp_i2c_mctrlw bits. i 2 c m aster and s lave c ontrollers i 2 cmaster module software interface btv2115 brook t ree 147 bt example bit setting sequence the following is a sample interaction between system software and the i 2 c master module that results in the i 2 c master module writing the value 3fh to the 7-bit ad- dress 1ah on the i 2 c bus. 1 first the system software checks for an idle condition on the i 2 c bus by reading the grp_i2c_mctrlr register, as illustrated below. note, the i 2 c master module is idle when mast = 0. however, this does not mean that the i 2 c bus is idle; the master module simply does not own the i 2 c bus and is not transmitting / receiving on it at the moment. if mast = 1, the grp_i2c_mctrlr register might contain the settings shown below. here, the i 2 c master module currently owns the i 2 c bus (mast = 1) but is idle at the moment (done = 1). any value other than 1 in done would mean that the i 2 c master module is currently processing a transmit or receive at the moment. the bits ?ld will indicate which bit it is currently working on: 0000 = msb, 0111 = lsb, 1000 = ack bit, etc. table 86. example of writing to grp_i2c_mctrlw unused 400k tsto tsta inte tack recv tran description 01000000do nothing. 00000000do nothing, in 100khz mode. 01011001t ransmit data preceded with start token. generate interrupt when done. 01000110 receive data into acknowledge. no interrupt when ?ished. 01100000t ransmit a stop token to release i 2 c bus 11000000 illegal: unused bit must not be 1 01000011 illegal: recv and tran = 1 01110000 illegal: tsta and tsto = 1 01100010 illegal: tsta and recv = 1 done lost rack mast bits grp_i2c_mctrlr 1 x x 0 1001 done lost rack mast bits grp_i2c_mctrlr 1 0 x 1 1001 i 2 c m aster and s lave c ontrollers i 2 cmaster module software interface btv2115 brook t ree 148 bt 2 the system software can set up the ?st data to be transmitted by writing 34h to the grp_i2c_mdata register. the value 34h is calculated by combining the 7 bit address 1ah in the 7 msbs with a 0 (write) in the r/w (lsb) ?ld, as shown below. 3 next the system software can start the transmit process by writing the following data to the grp_i2c_mctrlw register, as shown below. this con?uration requests the i 2 c master module to transmit a start token fol- lowed by the data in the grp_i2c_mdata register, generating an interrupt when the acknowledge has been received for this transmission. note that the system soft- ware must write ??to the unused ?ld to allow future extensions. 4 the i 2 c transmit will now proceed without interaction with the system software. if the system software had not enabled the interrupt, it would need to monitor the progress of the transmit by reading the grp_i2c_mctrlr register and taking further action when the transmit ?ishes. if software polling is used instead of interrupts and if the i 2 c master module is not serviced for a long period of time after the current transmit / receive is complete, the i 2 c bus will be idled thereby locking out any other potential i 2 c bus masters until the system software gives the i 2 c master module a new command. no data would be lost; just i 2 c bus bandwidth would be wasted. example bit setting sequence the following is the sequence of events the system software would see if it was monitoring the status of the i 2 c master module by reading the grp_i2c_mctrlr register. 1 initially the i 2 c master module would be waiting for an opportunity to transmit the start token (another i 2 c master module might currently own the bus). while this is the case, the grp_i2c_mctrlr register contains the following. msb lsb grp_i2c_mdata 0 0110100 unused 400k tsto tsta inte tack recv tran grp_i2c_mctrlw 0 1011001 done lost rack mast bits grp_i2c_mctrlr 0 0 x 0 0000 i 2 c m aster and s lave c ontrollers i 2 cmaster module software interface btv2115 brook t ree 149 bt 2 the ??in mast indicates that the i 2 c master module has not yet gained owner- ship of the i 2 c bus. once the i 2 c master has ownership (mast = 1) of the i 2 c bus and transmitted the start token, the grp_i2c_mctrlr register contains the fol- lowing. 3 the ?000?value in bits indicates that the msb of the transmit is currently in progress. as more bits are transmitted the value in bits will increase, as shown below. 4 the ?011?value in bits indicates that 2 bits have been transmitted and that the third bit is in progress. if the i 2 c master module loses the bus arbitration process to any other master at any time during transmission, the grp_i2c_mctrlr reg- ister might read as follows. 5 the i 2 c master module lost the bus arbitration process (lost = 1) while transmit- ting the 4th bit (bits = 0100) in the current word. note that once the i 2 c master module lost the arbitration process, bus ownership is lost and the mast bit is reset to ?.?also when the arbitration process ends, the current transmission ends and the done bit is set, thereby generating an interrupt if the inte bit was set. note that is possible to lose an arbitration while transmitting an ack bit for a reception so that the following bit pattern is possible. 6 assuming that no arbitration loss occurs, the i 2 c master module would ?ish the lsb of the transmission and start receiving the acknowledge bit, as shown below. done lost rack mast bits grp_i2c_mctrlr 0 0 x 1 0000 done lost rack mast bits grp_i2c_mctrlr 0 0 x 1 0011 done lost rack mast bits grp_i2c_mctrlr 1 1 x 0 0100 done lost rack mast bits grp_i2c_mctrlr 1 1 x 0 1000 done lost rack mast bits grp_i2c_mctrlr 0 0 x 0 1000 i 2 c m aster and s lave c ontrollers i 2 cmaster module software interface btv2115 brook t ree 150 bt 7 when the acknowledge bit is received, an interrupt will be generated and the trans- mit is complete. 8 the i 2 c master module is now ready for the next action. the system software would now write the value 3fh into the grp_i2c_mdataw register for the next i 2 c transmit. 9 the system software would again initiate the transmit by writing the following to the grp_i2c_mctrlw register. this con?uration is the same as before except the tsta bit is now ?,?indi- cating no start token is sent. 10 the system software is interrupted at the end of the transmit; assuming no arbitra- tion loss, the grp_i2c_mctrlr register again reads as follows. 11 the system software requests the sending of a stop token by writing the following to the grp_i2c_mctrlw register. note that this time the inte bit is ?,?disabling interrupts. the i 2 c master module would proceed to transmit a stop token but would not inform the system software with an interrupt when complete. done lost rack mast bits grp_i2c_mctrlr 1011 1001 msb lsb grp_i2c_mdata 0 0110100 unused 400k tsto tsta inte tack recv tran grp_i2c_mctrlw 0 1001001 done lost rack mast bits grp_i2c_mctrlr 1011 1001 unused 400k tsto tsta inte tack recv tran grp_i2c_mctrlw 0 1010000 i 2 c m aster and s lave c ontrollers i 2 cslave module software interface btv2115 brook t ree 151 bt i 2 c slave module software interface the software interface to the i 2 c master block is via 2 vga graphics extension registers: the grp_i2c_sctrl register (index 4ch) and the grp_i2c_sdata register (index 4dh). the grp_i2c_sdata register is read-only (since this mod- ule is a slave receiver only and cannot transmit). the grp_i2c_sctrl register is both read and write and behaves differently in each case. consequently, the soft- ware interface actually consists of one write-only register and two read-only reg- isters. in general, it is necessary to access both the grp_i2c_sctrl and grp_i2c_sdata registers at least once per byte of data received. the order of reading registers is important; the data received in the grp_i2c_sdata register should not be considered valid until after the done bit has been read as ??in the grp_i2c_sctrlr register. similarly the grp_i2c_sctrlw register should not be written until after the relevant data has been read from the grp_i2c_sdata register because writing to this register could initiate another data reception, thereby overwriting the data in the grp_i2c_sdata register. note that this i 2 c slave module is capable of losing the arbitration process just like the i 2 c master module. however this can only happen during transmission of the acknowledge bit. it is the responsibility of the system software to handle any problems like this that occur. the software interface to the i 2 c slave module is via the following registers. i 2 c slave data register name: grp_i2c_sdata index: 4dh, read only size: 8 bit function: the grp_i2c_sdata register supplies the contents of the input data buffer containing data received over the i 2 c bus. if this register is read while data reception is still in progress, the data read will be incorrect (not all bits will be shifted-in yet). it is the responsibility of the system software to wait until the data reception on the i 2 c bus is complete be- fore considering the data read from the grp_i2c_sdata register to be correct. data reception is complete when the done bit in the grp_i2c_sctrlr register contains a ?. the bit contents for the grp_i2c_sdata register are shown in ta- ble 87. table 87. i 2 c slave receive data grp_i2c_sdata bit function detail 7:0 data received data byte i 2 c m aster and s lave c ontrollers i 2 cslave module software interface btv2115 brook t ree 152 bt i 2 c slave control read register name: grp_i2c_sctrlr index: 4ch, read only size: 8 bit function: the grp_i2c_sctrlr register supplies status information about the progress / completion of any i 2 c bus transaction. a break must be en- abled before the i 2 c slave can supply status information; see table 91 on page 155. the bit contents for the grp_i2c_sctrlr register are shown in table 88. grp_i2c_sctrlr[7] (done) the done bit is set to ??whenever the i 2 c slave module has ?ished its current operation and is ready for another request from the system software. it is ? whenever the i 2 c slave module is busy servicing a request. this bit can be used by the system software to determine whether the i 2 c slave module was the source of an interrupt (interrupts enabled) or to check whether the i 2 c slave has ?ished its current request (software polling, interrupts disabled). this bit is used in the gen- eration of the i 2 c interrupt (it is anded with the inte interrupt enable bit) but it is set independently of the value of inte (interrupt enable). if more than one break request is included in the write to the grp_i2c_sctrlw register, the done bit will be set when a break conditions occurs. for each of the break conditions, the done bit will be set under the following conditions. bsta = 1: (break on start) the done bit will be set after the start token is received. brcv = 1: (break on receive) the done bit will be set after 8 data bits are received. this request facilitates the system software dynamically, determining the value of the ack bit to be transmitted based on the data received. table 88. i 2 c slave read control register grp_i2c_sctrlr bit function detail 7 done 0 = module is still busy with last request 1 = ?ished last request 6 lost 0 = arbitration not lost 1 = arbitration lost 5 stop 0 = no stop token received since last read 1 = stop token received since last read 4 mast 0 = bus idle 1 = some module is i 2 c master 3:0 bits current bit. see table 89. i 2 c m aster and s lave c ontrollers i 2 cslave module software interface btv2115 brook t ree 153 bt back = 1: (break on acknowledge) the done bit will be set after the acknowledge bit has been transmitted. this request facilitates the system software predetermining the value of the ack bit before any data has been received. bsto = 1: (break on stop) the done bit will be set after the stop token is received. finally, the done bit will also be set if the i 2 c bus arbitration is lost. grp_i2c_sctrlr[6] (lost) arbitration lost. the lost bit is set to 1 whenever the i 2 c slave module loses the i 2 c arbitration process. note, since this module is only capable of i 2 c receptions, it can only lose the arbitration process during the transmission of the acknowledge bit grp_i2c_sctrlr[5] (stop) stop token received. the stop bit indicates that a stop transaction was received on the i 2 c bus. this bit is cleared whenever the grp_i2c_sctrlw register is written. therefore if this bit is set, a stop transaction was received since the last grp_i2c_sctrlr write. grp_i2c_sctrlr[4] (mast) some module is master. a mast bit value of ??indicates that some i 2 c master module is the current bus master. in order to detect a reception or stop transaction on the i 2 c bus, this bit must be set. if this module is reset (mast = 0) while some other i 2 c master module is driving the i 2 c bus, this module will not be able to re- ceive data or detect a stop transaction until after the current i 2 c transaction is com- pleted. grp_i2c_sctrlr[3:0] (bits) current bit being processed. the bits value indicates the number of the bit cur- rently being processed during a receive, as shown in table 89. do not assume that an i 2 c reception is ?ished until this ?ld contains the value of 9 (?001?. how- ever, the correct way to detect the completion of an i 2 c transaction when the done status bit = 1. this ?ld is actually the contents of an internal counter within the i 2 c master module that counts the number of bits received. table 89. grp_i2c_sctrlr current bit bits[3:0] value meaning 0000 0 1 st bit in progress 0001 1 2 nd bit in progress ... ... ..... 0110 6 7 th bit in progress 0111 7 8 th bit in progress 1000 8 ack bit in progress 1001 9 all bits done i 2 c m aster and s lave c ontrollers i 2 cslave module software interface btv2115 brook t ree 154 bt below, table 90 shows an example of possible settings of the grp_i2c_mctrlr bits. i 2 c slave control write register name: grp_i2c_sctrlw index: 4ch, write only size: 8 bit function: the grp_i2c_sctrlr register controls the operation of the i 2 c slave module. writing to this register initializes the done and bits ?lds in the grp_i2c_sctrlr register. initializing the bits ?ld in the grp_i2c_sctrlr register would destroy any i 2 c bus transac- tion in progress, so this register must not be written to while the i 2 c slave module is busy. it is the responsibility of the system software to ensure that this register is never written to except when the i 2 c master module is idle (indicated by done = 1 in the grp_i2c_sctrlr reg- ister). all the bits in this register except for tack are set to zero upon re- set. this reset initialization places the i 2 c slave module in an idle state immediately after reset. the tack value of ??is transmits an ack bit of ?,?which indicates a ?ot acknowledge?state. with these reset values in the grp_i2c_sctrlw register, the i 2 c slave module will receive data from the i 2 c bus as it appears but it will never transmit any i 2 c acknowledge bits and it will never generate an interrupt. a break (bsto, bsta, brcv, or back) must be enabled so that the slave state machine operates properly. a break acts as an interrupt causing the slave to hold sclk low, stretching the cycles until re- leased. the next start or stop will reset the slave. the bit contents of the grp_i2c_sctrlw register are shown in table 91. table 90. examples of reading grp_i2c_sctrlr done lost stop mast bits description 1 x0 0 xxxx idle, not bus master. this module idle. 0 x0 0 xxxxi 2 c bus idle. this module busy (waiting for start, etc.). 00010100i 2 c bus not idle. this module busy (receive in progress, 3 bits done). 10011001i 2 c bus not idle. this module done. 11011000i 2 c bus not idle. lost arbitration on ack bit of last receive 1011 xxxxi 2 c bus not idle. stop received since last read. i 2 c m aster and s lave c ontrollers i 2 cslave module software interface btv2115 brook t ree 155 bt grp_i2c_sctrlw[7:6] these bits are currently unused in the i 2 c slave module, however the system soft- ware must always write ?0?here to allow for possible future expansions. grp_i2c_sctrlw[5] (bsto) break on stop. when set to ?,?this control bit causes this module to generate a done bit/interrupt after the next stop token reception on the i 2 c bus. grp_i2c_sctrlw[4] (bsta) break on start. when set to ?,?this control bit causes this module to generate a done bit/interrupt after the next start token reception on the i 2 c bus. grp_i2c_sctrlw[3] (inte) interrupt enable. when set to ?,?this control bit causes the interrupt output from the i 2 c slave module to go to ??whenever the contents of the done ?ld goes to ?.?if this bit is set to ?,?the system software must service this module by means of software polling. this process will not result in the loss of any data but may cause the i 2 c bus idle until the system software next polls this module and sets up the next request. note that the actual interrupt is generated by anding this bit with the done bit of the ctrlr read register. grp_i2c_sctrlw[2] (tack) ack bit to transmit. this is the value that the i 2 c slave module will transmit whenever it needs to transmit an acknowledge bit. (i.e. whenever it needs to ac- knowledge a i 2 c reception.) grp_ i_i2c_sctrlw[1] (brcv) break on receive. when written with ?,?this bit will cause this module to gener- ate a done bit/interrupt after the next end of receiving 8 bits of data. table 91. i 2 c slave write control register grp_i2c_sctrlw bit function detail 7:6 reserved must write 0 s here 5 bsto 0 = no break after receive stop 1 = break after receive stop 4 bsta 0 = no break after receive start 1 = break after receive start 3 inte 0 = disable interrupt (software polling) 1 = interrupt enable 2 tack 0 = value to transmit for ack bit 1 = no ack value to transmit 1 brcv 0 = no break after receive data 1 = break after receive data 0 back 0 = no break after transmit ack 1 = break after transmit ack i 2 c m aster and s lave c ontrollers i 2 cslave module software interface btv2115 brook t ree 156 bt grp_i2c_sctrlw[0] (back) break on acknowledge. when set to ?,?the bit will cause this module to generate a done bit/interrupt after the next transmission of the acknowledge bit. determining break condition you can combine several of the possible break requests into a single request to the i 2 c slave module; the interrupt will be generated whenever the ?st break condi- tion occurs. if more than one break condition is speci?d, it is usually possible upon receipt of the interrupt to determine which break condition caused the inter- rupt by reading the grp_i2c_sctrlr register. the bsta (break on start) request sets mast=1 and bits=0000 in the grp_i2c_sctrlr register. the brcv (break on receive) request sets mast=1 and bits=1001 in the grp_i2c_sctrlr register. the data received can be read from grp_i2c_sdata, and the acknowledge bit to be transmitted can be controlled by writing to the tack bit of the grp_i2c_sctrlw register. the back (break on acknowledge) request sets mast=1 and bits=1001 in the grp_i2c_sctrlr register. the data received can be read from grp_i2c_sdata. the bsto (break on stop) request sets stop=0 in the grp_i2c_sctrlr register, indicating that the interrupt was generated by a stop transaction on the i 2 c bus. using this break condition to generate interrupts which will be used by soft- ware is an inherently dangerous procedure. unlike all the other ?reak on some- thing?conditions, bsto does not hold the i 2 c bus to wait for service from the software interrupt service routing (the i 2 c spec won t allow this). this is especial- ly dif?ult in a polled (i.e. interrupts disabled) environment because a signi?ant period of time might pass before the i 2 c module is polled. if this happens and if the interrupt is not serviced in time, the i 2 c bus could continue off into another trans- action, the start of which would be missed by the btv2115 i 2 c slave module. minimum stop transaction the i 2 c spec guarantees a minimum of 1.3 m s between a stop transaction and a fol- lowing start transaction on the i 2 c bus, so if the software interrupt service routing can guarantee to service the interrupt in less than 1.3 m s there won t be a problem. if there is any doubt that the software interrupt service routine can service a break on stop interrupt quickly enough then the break on stop condition must be com- bined with another break request (break on start, break on receive or break on ac- knowledge) to allow the i 2 c slave module to continue with the next reception without loss of data. when this is done the software interrupt service routine must check for the possibility that both break conditions (break on stop and the other break condition) have occurred when servicing the interrupt and take appropriate action if the second break condition has also occurred to avoid missing the second interrupt. note also that any of the above break conditions except for bsto (break on stop) will cause the i 2 c slave module to hold the i 2 c bus idle until the grp_i2c_sctrlw register is written again with a new request. it is the respon- sibility of the system software to ensure that the grp_i2c_sctrlw register is written to un-idle the i 2 c bus within a reasonable period of time. the system soft- ware is also responsible for ensuring that the i 2 c slave module is given a new re- i 2 c m aster and s lave c ontrollers i 2 cslave module software interface btv2115 brook t ree 157 bt quest suf?iently fast after a break on stop condition. this is necessary because the break on stop does not idle the i 2 c bus, which could therefore begin another trans- action while the i 2 c slave module is still waiting for system software service, caus- ing the loss of data. fortunately it is never necessary to detect a break on stop condition in the normal operation of the i 2 c; the system software could easily ig- nore the stop token and instead break on start to detect the start of the next i 2 c bus transaction. also, the i 2 c spec requires that the i 2 c bus remain idle for 1.3 m s after the transmission of a stop token, guaranteeing the system software at least 1.3 m s to respond to the break on stop request. passive i 2 c bus snooper it is possible to use the i 2 c slave module as a completely passive i 2 c bus snooper. set the grp_i2c_sctrlw register to break at the various points of interest in the i 2 c transactions and set the tack bit to ?.?data is received as in normal i 2 c slave module operations, but you can also see what value ack bit was transmitted by looking at the value of the lost bit in the grp_i2c_sctrlr register. if the ack bit on the i 2 c bus was ?,?the lost bit will be set to ??(since the i 2 c slave module was trying to send an ack of 1 and saw an ack of ?,?it sets the lost bit). similarly an ack bit of ??on the i 2 c bus will cause the lost bit in the grp_i2c_sctrlr register to remain at zero. to ensure that the i 2 c slave module is completely passive, all the ?reak on something?conditions must be serviced immediately. polling or interrupting is not suf?ient because the i 2 c slave module might halt the i 2 c bus if it is left waiting for software service for too long. below, table 92 shows an example of possible settings of the grp_i2c_sctrlw bits. example bit settings sequence the following is a sample interaction between system software and the i 2 c slave module during which the i 2 c slave module receives a series of bytes of data. after the reception of the ?st two bytes the system software is able to determine that this i 2 c module is not being addressed by the current i 2 c transaction and ignore the rest of the transaction. table 92. example of writing to grp_i2c_sctrlw unused bsto bsta inte tack brcv back description 00000000do nothing 00001000 pointless: no break requested so no interrupt will be generated 00011010 interrupt upon reception of a start token or 8-bits of data 00001001 receive 8 bits of data acknowledge with ack=0, then interrupt 00111000 interrupt upon reception of start or stop token 10000000 illegal: unused bit not ? i 2 c m aster and s lave c ontrollers i 2 cslave module software interface btv2115 brook t ree 158 bt 1 first the system software checks whether the i 2 c bus is idle by reading the grp_i2c_sctrlr register. here it can be seen that the i 2 c bus is idle (mast = 0). note that unlike the mast bit in the grp_i2c_mctrlr register of the i 2 c master module, this bit indicates whether the i 2 c bus is idle. in the i 2 c master module, the mast bit in- dicates whether the i 2 c master module is currently bus master. if the i 2 c bus is currently busy (mast = 1), the grp_i2c_sctrlr register might contain the following settings. any value other than ??in done would mean that the i 2 c slave module is currently processing a request. during data reception, the bits ?ld will indicate which bit is currently being received: 0000 = msb, 0111 = lsb, 1000 = ack bit being transmitted, etc. 2 the system software can then set up the ?st request to be processed by writing 0ah to the grp_i2c_sctrlw register. this value will generate an interrupt once 8 bits of data has been received. 3 the i 2 c slave module can now proceed without interaction with the system soft- ware. if the system software had not enabled the interrupt, it would need to moni- tor the progress of the transmit by reading the grp_i2c_sctrlr register and taking further action when the reception ?ishes. if software polling is used instead of interrupts and if the i 2 c slave module is not serviced for a long period of time after the current receive is complete, the i 2 c bus will be idled thereby lock- ing out any other i 2 c traf? until the i 2 c slave module interrupt is serviced. except for the case of detecting stop tokens mentioned above (which can be avoided by correct design of the system software), no data would be lost because of delayed servicing of i 2 c slave module interrupts / done bits - just i 2 c bus bandwidth would be wasted. the following is the sequence of events the system software would see if it was monitoring the status of the i 2 c slave module by reading the grp_i2c_sctrlr register. done lost stop mast bits grp_i2c_sctrlr 1 x 0 0 1001 done lost stop mast bits grp_i2c_sctrlr 1001 1001 unused bsto bsta inte tack brcv back grp_i2c_sctrlw 0 0 0 0 1 0 1 0 i 2 c m aster and s lave c ontrollers i 2 cslave module software interface btv2115 brook t ree 159 bt initially the i 2 c slave module would be waiting for an i 2 c master module to be- come bus master and transmit a start token. while this was the case, the grp_i2c_sctrlr register would contain the following. the ??in mast indicates the i 2 c bus is still idle. once some i 2 c master gets ownership of the i 2 c bus and transmits the start token the grp_i2c_sctrlr register would read as follows. the ??in mast indicates that some i 2 c master module now owns the i 2 c bus. the ?000?value in bits indicates that the msb of the transmit is currently in progress. as more bits are received the value in bits will increase, as shown be- low. the ?011?value in bits indicates that 2 bits have been received and that the third bit is in progress. once all 8 bits have been received, an interrupt will be gen- erated. the i 2 c slave module will idle the i 2 c bus while waiting for service by the system software. 4 when responding to the interrupt, the system software can check the progress of the i 2 c reception by reading the grp_i2c_sctrlr register, as shown below. the ??in the done bit indicates the i 2 c slave module has ?ished the last re- quest. mast = 1 indicates the i 2 c bus is busy. and bits = 1000 indicates that all 8 bits of data have been received. the system software can see the data received by reading the grp_i2c_sdata register. then it can setup the i 2 c slave module to receive the next byte of data by again writing 0ah to the grp_i2c_sctrlw register. this value will transmit an acknowledge bit of ?,?then generate an interrupt once an- other 8 bits of data has been received, as shown below. done lost stop mast bits grp_i2c_sctrlr 0 0 x 0 xxxx done lost stop mast bits grp_i2c_sctrlr 0 0 x 1 0000 done lost stop mast bits grp_i2c_sctrlr 0 0 x 1 0011 done lost stop mast bits grp_i2c_sctrlr 1 0 x 1 1000 unused bsto bsta inte tack brcv back grp_i2c_sctrlw 0 0 001010 i 2 c m aster and s lave c ontrollers i 2 cslave module software interface btv2115 brook t ree 160 bt once all 8 bits have been received, an interrupt will be generated. the i 2 c slave module will again idle the i 2 c bus while waiting for service by the system soft- ware. 5 when responding to this interrupt, the system software can again check the progress of the i 2 c reception by reading the grp_i2c_sctrlr register, as shown below. this indicates that the i 2 c slave module has done the last request, that the i 2 c bus is busy and that 8 bits of data has been received. the system software can see the data received by reading the grp_i2c_sdata register. at this stage the system software can determine that the current i 2 c bus transaction is addressed to some other i 2 c slave module. it can instruct the i 2 c slave module to not acknowledge this byte by transmitting an ac- knowledge value of ??and to ignore all further i 2 c activity until the next start to- ken by writing 1ch to the grp_i2c_ sctrlw register, as shown below. the i 2 c slave module will ignore all transactions on the i 2 c bus until it next sees a start token. it will then generate another interrupt and will idle the i 2 c bus while it waits for service by the system software. 6 the system software can begin again with the new i 2 c transaction by again writing 0ah to the grp_i2c_ sctrlw register, requesting an interrupt at the end of reception of the 8 bits of data. done lost stop mast bits grp_i2c_sctrlr 1 0 x 1 1000 unused bsto bsta inte tack brcv back grp_i2c_sctrlw 0 0 011100 brook t ree 161 bt gui a ccelerator gui theory of operation to better understand this chapter, ?st read ?ntroduction?on page 97 and ?ro- tected mode aperture?on page 101 in the ?pu address space apertures?chap- ter. the btv2115 mediastream controller consists of a programming interface sec- tion and an autonomous drawing engine capable of performing bitblt, character rasterization, line draw, and stretchblt. the command interface to the accel- erator is completely queued through a buffer management and command pacing mechanism that requires essentially no reads from the gui unless expressly trans- ferring a pixmap from the frame buffer to the cpu. the gui accelerator registers, commands, and parameters are transferred through the lower six mb of the pro- tected mode aperture. see ?ui command/register map?on page 112 for a dis- cussion of the queueing mechanism. retained bitmap context one of the acceleration features provided is the caching of bitmap context for the screen as well as for up to three off screen bitmaps. in addition, type information is retained for up to four bitmaps residing in host memory. source and destination pixmaps are ef?iently identi?d with a command as selectors of these eight re- tained pixmap register contexts, see ?itmap context registers?on page 173 for additional discussion on the 8 sets of bitmap context caching registers. raster operation the btv2115 gui has a two-operand raster-op engine which logically combines a source and a destination operand. there are sixteen possible combinations; the se- lection of the desired operation is controlled by a ?e bit ?ld in the gui con?u- ration register, as shown in the rop code ?ld of table 107. each command has a copy and a rop version. when the copy version is used, no logical combi- nation is performed; the source is always copied to destination. when the rop ver- sion is used, the logical operation selected by the control value is performed. one of the sixteen operations is copy, so this operation can be performed either way. in addition, the source can be any valid source bitmap: solid colors, patterns, host (mono and color), offscreen, and screen. gui a ccelerator gui theory of operation btv2115 brook t ree 162 bt communication of gui commands, parameters, and register values are paced to the accelerator such that all register modi?ations which follow a command will be held until that command is completed. for example, the procedure to draw ?e line segments in ?e different colors is as follows (assuming the appropriate set- up). five pairs of foreground register values and their line draw commands are sent. if the accelerator is idle when the ?st foreground register value is supplied, it will immediately load the foreground color register. when the accelerator re- ceives the ?st line draw command and its associated parameters, it will go busy and remain that way until completion of the line draw. if the second foreground register value is received while the accelerator is busy, the value is held in the queue until the accelerator goes idle. at this time the new color value is loaded into the foreground register. when the accelerator receives the second line draw com- mand and parameters (either from the cpu or the queue), it will go busy and com- mence drawing. this sequence is repeated until all ?e lines are drawn in ?e different colors. since each command contains a selector for the bitmap cached context, the lines could also be directed to different destinations with the extents, pitches, and pixel depths automatically managed by the hardware. notice that any drawing operation can reference host bitmaps as a destination however, only the blt drawing operator referencing host bitmaps as a destination makes any useful sense. gui a ccelerator cpu addressing of gui btv2115 brook t ree 163 bt cpu addressing of gui the 32 bit cpu address controls the gui queued interface, shown in figure 18. when the following signal conditions are met, cpu address bits 21:2 are used as a selector to determine an action for the memory read or write command. cpu address bits 31:25 match the value of gui_base[31:25] (pm_base ?ld) gui_base[24] (pm_enable ?ld) is set to 1 cpu address bits 24:22 are set to zero the meaning of the selector address bits 21:2 is found in table 93, which shows that cpu address bits 21:16 de?e the gui command to be performed. table 93 further shows that there is a different de?ition for the lower 16 address bits de- pending on whether the command is a drawing operation, a register access, or a data transfer. table 94 maps the selector bits 21:16 to a speci? gui command and shows the types of commands supported by the accelerator. figure 18. queued gui address mapping queued gui 0 1 2 21 . . . gui selector map note: [1:0] de?ed by byte enables, always 4 byte 0 1 2 21 24 31 23 22 . . . . . . 25 gui_base 0 31 cpu address hbus address/control 4m 8m 32m 0 0 0 gbase[31:25] 4 mb address 24 25 23 22 21 1 2 match protected mode accessed gui a ccelerator cpu addressing of gui btv2115 brook t ree 164 bt notice in table 93 that register accesses occupy the ?st 64kb of the gui ac- cess space. this is the queued method of register access described above in which register loads are guaranteed to behave in strict sequential order with respect to the drawing operations. the register access commands are repeated at gbase+4mb where they are not queued (a register write will occur immediately regardless of whether the accelerator is busy or idle). it is generally too dangerous to access gui accelerator registers using the non-queued address space while the accelerator is busy. the non-queued method is used for various non-accelerator registers, which are de?ed in ?ui command/register map?on page 112 of the ?pu address space apertures?chapter. the non-queued guireg_mba register controls the type of bit, byte, word, and dword ?pping occurs throughout the flippin map of the protected mode aperture and is relatively unrelated to gui accelerator com- mand queueing. however during driver initialization, this register is loaded with a value that controls whether gui commands/register/data access are big endian or little endian . shown in table 93, a bit ?ld is reserved within both drawing operation ad- dresses and data word transfer addresses so that addresses from a rep movsd in- struction can ?oll?through the parameters. thus you can keep the basic command address in the program, load it into edi (a 32-bit offset register), then pass out 8k dwords of host-to-screen blt data using the address roll ?ld. thus a drawing command could be started at any one of eight possible addresses corre- sponding to one of the values of the parameter address roll field. whether a dword is a command or a parameter is not encoded in this ?ld. the two are distinguished by their placement in the transfer sequence relative to the previously issued command. every dword comes over the bus in one cycle and contains an address and a data ?ld. the ?st parameter (if any) accompanies the table 93. address fields for gui accesses cpu address bits field description gui selector # register access cpu-gui data transfers drawing operations 21:16 gui command number = 6?000000 gui command number = 6?000001 gui command number > 6?000001 15:14 unused 1-16k data dword address roll ?ld reserved 13:11 ? source bitmap selector 10:8 ? destination bitmap selector 7:5 register number parameter count 4:2 parameter address roll field 1:0 always set to zero, i.e. a 32 bit transfer ? see table 102 on page 174 gui a ccelerator cpu addressing of gui btv2115 brook t ree 165 bt ?st address ?ld. for example, if a drawing command was issued with parameter count 2, the next command of whatever type will appear as the second dword fol- lowing the drawing command. reads from the queued map are unsupported because they have the potential to hang the cpu for very long periods of time. consequently, to read the ?al state of the destination xy increment register, the gui must be completely idle before issuing a non-queued read using the access shown in figure 19. because of this hang potential and because a read operation to most of the ?st 4mb has no mean- ingful de?ition, you should always read through the non-queued interface. if reading gui accelerator registers or screen- cpu data, ?st use the status bits in ?ui fifo depth register?on page 114 to insure that the accelerator is complete- ly idle or actually has read data ready before issuing the ?st read. once the accel- erator has the ?st read data word available, driver programs can use rep movs instructions to transfer data from screen to host cpu. the accelerator will pace the cpu via the ready line and will, in general, keep up with the cpu demand. figure 19. non-queued gui address mapping non-queued only register r/w and data read are de?ed in the non-queued address map. 0 1 2 21 . . . gui selector map note: [1:0] de?ed by byte enables, always 4 byte 0 1 2 21 24 31 23 22 . . . . . . 25 gui_base 0 31 cpu address hbus address/control 4m 8m 32m 0 0 1 gbase[31:25] 4 mb address 24 25 23 22 21 1 2 match protected mode accessed gui a ccelerator cpu addressing of gui btv2115 brook t ree 166 bt for drawing operations, variable numbers of parameters are permitted (encour- aged) using the count mechanism in the command ( vl / pci address bus bits). a zero or one parameter command takes one bus cycle to transfer the command and optional parameter. a two parameter command takes exactly two bus cycles, etc. in addition, a one parameter command takes two word locations in the vram fifo, etc. when commands are inserted into the vram queue software must know how many dwords will be occupied so that the queue depth can be accurately modeled to prevent over?w. table 94, ?ui commands,?on page 167 shows how to com- pute the number of vram gui queue dwords will be occupied by each command for a given number of parameters or data dwords in the gui quesize expression. gui a ccelerator gui commands btv2115 brook t ree 167 bt gui commands the gui commands are listed in table 94 and de?ed in the following pages. the gui command number is determined by cpu address bits [21:16] (see table 93). table 94. gui commands (1 of 2) gui command number command raster ops no. of parms. queued access non- queued access description 000000 rw register n/a n/a write read write read or write one of 64 gui registers. this command is also available through the non-queued map described above. notice that all writes are queued in sequence with their corresponding gui commands, e.g. blt. notice also that no reads are queued. (gui quesize = 2). see ?wregister command?on page 168. 000001 rwgui data n/a n/a write read this command allows data to pass to or from the host cpu. on the ?st cycle of a write the data bus contains a count of the number of dwords to be sent with subsequent rw gui data commands. (gui quesize = #dwords+1). see ?wguidata command?on page 170. 000010- 101111 reserved n/a n/a none none 110000 stretch blt copy 0-4 write none (gui quesize = #parameters +1) 110001 trap (reserved) copy 110010 line copy 0-2 write none (gui quesize = #parameters +1) 110011 bitblt copy 0-3 write none (gui quesize = #parameters+1) 110100 stretch blt copy trans- parent 0-4 write none (gui quesize = #parameters +1) 110101 trap (reserved) copy trans- parent gui a ccelerator gui commands btv2115 brook t ree 168 bt rwregister command if we de?e a c constant to reference the queued register map, it could be coded: #define queued_reg 0x00000000 to access the guireg_mba register through the queued register interface we could form an address such as: ((unsigned long *)(gbase| queued_reg | guireg_mba)) we can also de?e a c constant to reference the non-queued register map: #define non_queued_reg 0x00400000 to access the guireg_mba register through the non-queued register interface we could form an address such as: (unsigned long *)(gbase| non_queued_reg | guireg_mba) four drawing operators are de?ed for the gui accelerator, namely bitblt, rwguidata, line, stretchblt, discussed below. 110110 line copy trans- parent 0-2 write none (gui quesize = #parameters +1) 110111 bitblt copy trans- parent 0-3 write none (gui quesize = #parameters+1) 111000 stretch blt rop 0-4 write none (gui quesize = #parameters +1) 111001 trap (reserved) rop 111010 line rop 0-2 write none (gui quesize = #parameters +1) 111011 bitblt rop 0-3 write none (gui quesize = #parameters+1) 111100 stretch blt rop trans- parent 0-4 write none (gui quesize = #parameters +1) 111101 trap (reserved) rop trans- parent 111110 line rop trans- parent 0-2 write none (gui quesize = #parameters +1) 111111 bitblt rop trans- parent 0-3 write none (gui quesize = #parameters+1) table 94. gui commands (2 of 2) gui command number command raster ops no. of parms. queued access non- queued access description gui a ccelerator gui commands btv2115 brook t ree 169 bt bitblt command many different blt operations can be very simply encoded with the btv2115 blt mechanism. because the source and destination bitmap context selector within the command can point to either host or media buffer bitmaps, all opera- tions can be speci?d quite succinctly. a blt command can be accompanied by up to three parameters so that a maximum blt command is de?ed in table 95. the destination xy address speci?s the xy offset into the bitmap of the ?st pixel to be written. the xy extents specify the width and height of the rectangle to be written. the source xy address speci?s the xy offset into the source bitmap. in the case of a bitmap in cpu memory, the x value is used to determine the alignment relative to the destination array. the y value is not used. in the case of a pattern as the source, the x and y values provide the starting offset into the pattern. patterns are stored in packed dword format, e.g. a monochrome 8x8 pattern is stored as two consecutive dwords in the frame buffer. the lowest-addressed ele- ment of each line of the pattern is the ?st pixel displayed for each line of the pat- tern. in other words, the right-most or least signi?ant element becomes the left- most pixel. patterns are aligned relative to the offset frame buffer origin rather than to the starting destination address. the effect is that no matter where a pattern ?l is start- ed, the same pixels are drawn in the destination area as would have been if the pat- tern drawn had started at pixel (0,0) and continued to the destination area. the source ( x,y) address for a pattern ?l is always taken to mean the ( x,y) address of the ?st pixel of the ?st line of the complete pattern. when the source of the blt is a host bit map, an rwguidata command (gui command number 000001) must immediately follow the blt command which transfers up to 16 k dwords to the gui accelerator. it should be noted that whenever an xy address is speci?d in a parameter or register it has the format shown in table 96. table 95. blt command address bus data bus gui accelerator value blt dest xy address command + p0 parameter count and address roll ?ld are don? cares xy extents p1 parameter count and address roll ?ld are don? cares source xy address p2 gui a ccelerator gui commands btv2115 brook t ree 170 bt rwguidata command this command is used for host-to-screen or screen-to-host transfers only. table 97 shows the form that the rwguidata command takes for an n dword transfer. table 98 de?es the rwguidata_length variable. it is a programming er- ror to supply a rwguidata_length word for screen-to-host transfers. after sending the command, the host simply reads the required number of dwords from anywhere within the 16k dword rwguidata address roll space. table 96. xy address format bit(s) field name description 31:28 reserved must be set to zero 27:16 y address vertical index or row number 15:12 reserved must be set to zero 11:0 x address horizontal index or column number table 97. rwguidata command queue dword no. bitmap dword no. dword use 1 n/a rwguidata_length (host-to-screen only) 2 1 bitmap dword 1 3 2 bitmap dword 2 ... ... n n-1 bitmap dword n-1 n+1 n bitmap dword n table 98. rwguidata_length bits description 31:27 unused 26:16 # of y scan lines in source (host) bitmap (n-1) 15:12 unused 11:0 # of dwords per scan line in source (host) bitmap (n-1) gui a ccelerator gui commands btv2115 brook t ree 171 bt line draw command the line command (de?ed in table 99) supports both single and polyline capa- bilities. the end points of the line are both speci?d for single line commands. only the end point is speci?d for polylines in which case the starting point is the previous endpoint. notice that the ?ine control register?on page 180 contains control bits that determine whether the ?st or last pixels of a line segment will be skipped or drawn. also, this register determines several ?tyles?of bresenham line algo- rithms, including whether the line can be drawn reversibly. if no parameters are sent, i.e. parameter count ?ld = 0 in the command, then the line drawing registers are assumed to have already been set up (end points, error terms, etc.). notice that the ending xy (p0) unconditionally gets copied to startingxy (p1) after every line draw. stretchblt command this command is used to implement both stretch_blt and stretch_dib windows driver routines. table 100 de?es the stretch_blt. notice that for the stretch_blt command, parameter 3 can only specify an x extent by which to stretch since this command only handles horizontal stretch- ing. table 99. line command address bus data bus gui accelerator value line ending xy point command +p0 parameter count and address roll ?ld are don? cares starting xy point p1 table 100. stretchblt command address buss data bus gui accelerator value blt dest xy address command + p0 parameter count and address roll ?ld are don? cares dest xy extents p1 parameter count and address roll ?ld are don? cares source xy address p2 parameter count and address roll ?ld are don? cares source x extent p3 gui a ccelerator gui registers btv2115 brook t ree 172 bt gui registers table 101 lists the gui commands, their addresses, and descriptions. an address in the gui register is generated by oring the gbase value with the register ad- dress to create the offset address. note the gui enable bit in con?uration register (grp_cfg4 [0]) must be set before these registers can be accessed. table 101. gui registers (1 of 2) queued address (hex) non-queued address (hex) name description 00000000 00400000 parameter0 first parm of a command. this is a register rw view of the parameter which is normally sent as part of a command not as a register rw. 00000004 00400004 parameter1 second parm of a command. 00000008 00400008 parameter2 third parm of a command. 0000000c 0040000c parameter3 fourth parm of a command 0000001c 0040001c command last command value sent to gui. this is primarily for diag- nostic use 00000020 00400020 gui_fg_color ?oreground color register?on page 178 00000024 00400024 gui_bg_color ?ackground color register?on page 179 00000028 00400028 line_patt ?ine pattern register?on page 181 0000002c 0040002c gui_dst_xy_inc ?estination xy increment register?on page 179 00000030 00400030 gui_cfg ?ui con?uration register?on page 176 00000034 00400034 blt_control ?lt control register (direction)?on page 179 00000038 00400038 line_control ?ine control register?on page 180 00000040 00400040 bmap0_type ?itmap context registers?on page 173 00000044 00400044 bmap0_pitch ?itmap context registers?on page 173 00000048 00400048 bmap1_type ?itmap context registers?on page 173 0000004c 0040004c bmap1_pitch ?itmap context registers?on page 173 00000050 00400050 bmap2_type ?itmap context registers?on page 173 gui a ccelerator gui registers btv2115 brook t ree 173 bt bitmap context registers bmap[7:0]_type, bmap[7:0]_pitch ?there are eight pairs of 32-bit bitmap registers (bmap0_type and bmap0_pitch, bmap1_type and bmap1_pitch, etc.). registers bmap[3:0]_type contain both type and offset information. registers bmap[7:4]_type contain only type information. regis- ters bmap[3:0]_pitch contain pitch information. registers bmap[7:4]_pitch are used for host bitmaps and solid ?l functions and are not available for use (as indicated in table 101). 00000054 00400054 bmap2_pitch ?itmap context registers?on page 173 00000058 00400058 bmap3_type ?itmap context registers?on page 173 0000005c 0040005c bmap3_pitch ?itmap context registers?on page 173 00000060 00400060 bmap4_type only bits 29:24 are present 00000064 00400064 bmap4_pitch reserved (no pitch value) 00000068 00400068 bmap5_type only bits 29:24 are present 0000006c 0040006c bmap5_pitch reserved (no pitch value) 00000070 00400070 bmap6_type only bits 29:24 are present 00000074 00400074 bmap6_pitch reserved (no pitch value) 00000078 00400078 bmap7_type only bits 29:24 are present 0000007c 0040007c bmap7_pitch reserved (no pitch value) 00000080 00400080 bres0_addr ?resenham 0, address register?on page 182 00000084 00400084 bres0_err ?resenham 0, error register?on page 182 00000088 00400088 bres0_k1 ?resenham 0, k1 register?on page 182 0000008c 0040008c bres0_k2 ?resenham 0, k2 register?on page 183 00000090 00400090 bres0_inc1 ?resenham 0, increment 1 registers?on page 183 00000094 00400094 bres0_inc2 ?resenham 0, increment 1 registers?on page 183 00000098 00400098 bres0_length ?resenham 0, length register?on page 184 0000009c : 000000ec 0040009c : 004000ec reserved don? use 004000f0 guireg_mba ?ba control register?on page 125 don? use 004000f4 guireg_depth see ?ui fifo depth register?on page 114. don? use 004000f8 guireg_fifo see ?ui fifo register?on page 112. don? use 004000fc guireg_data diagnostic use only. within the chip, this code is used for the read/write gui data command. register transfers to/ from this location are unde?ed in normal operation. table 101. gui registers (2 of 2) queued address (hex) non-queued address (hex) name description gui a ccelerator gui registers btv2115 brook t ree 174 bt the contents of the bitmap context registers are shown in table 102. table 103 de?es the type ?ld. table 104 de?es the offset ?ld. table 105 de?es the pitch ?ld. the gui selector number is determined by the cpu address. bits [13:11] and [10:8] specify either a source or destination bitmap selector, respectively (see table 93 on page 164). as shown in table 103, the bitmap register type uses the saved context to tell the gui accelerator how to treat the speci?d source or destination bitmap. table 102. bitmap context registers gui selector # 32 bit register upper 8 bits [31:24] lower 24 bits [23:0] 000 bmap0_type type offset bmap0_pitch reserved pitch 001 bmap1_type type offset bmap1_pitch reserved pitch 010 bmap2_type type offset bmap2_pitch reserved pitch 011 bmap3_type type offset bmap3_pitch reserved pitch 100 bmap4_type type reserved bmap4_pitch reserved reserved 101 bmap5_type type reserved bmap5_pitch reserved reserved 110 bmap6_type type reserved bmap6_pitch reserved reserved 111 bmap7_type type reserved bmap7_pitch reserved reserved gui a ccelerator gui registers btv2115 brook t ree 175 bt table 106 shows an example of how the bitmap context registers might be allo- cated for one instant in the life of a windows driver. notice contexts 7:4 are either allocated to host bitmaps or constant source (src) data patterns. to change the drawing context, all the driver has to do is send bitmap context register changes down the vram queued register write path within the sequence of drawing oper- ations. suppose the sequence looks like: blt#1, queued write to context 1 offset, queued write to context 1 pitch, blt#2. suppose that both blt#1 and blt#2 use bitmap context 1 as their destinations (dst). blt#1 could be directed to a screen table 103. bitmap register type field bit(s) description 7:6 reserved 5:4 pattern size 00 = arbitrary (reserved in btv2115) 01 = 8x8 10 =16x16 11 = 32x32 3 1 = solid ?l with background color 2 1 = pattern 1 1 = host 0 1 = mono table 104. bitmap register offset field bits description 24:20 reserved 19:0 offset value. the bitmap s starting location in vram table 105. bitmap register pitch field bits description 31:12 reserved 11:4 ? pitch pixel value: 0010 0000 = 512 0100 0000 = 1024 0010 1000 = 640 0101 0000 = 1280 0011 0010 = 800 0110 0100 = 1600 0011 1001 = 912 1000 0000 = 2048 3:0 always 0 ? except for the 912, each line of bitmap/pattern must start on a dword boundary. gui a ccelerator gui registers btv2115 brook t ree 176 bt window while blt#2 could be directed to an offscreen bitmap. since drawing context is retained and since context changing register writes can be enqueued in sequence there is virtually no need for the windows driver to synchronize to the actual current drawing state of the gui accelerator. therefore the driver can pro- ceed far ahead of the hardware and allow full overlap of application execution with drawing setup and rasterization. if the source ( src ) bitmap has the host bit set but also has the solid ?l bit set or if a rop is speci?d that doesn t use src data, then it is a programming error to supply host data. unused src data will halt all data and command ?w through the gui fifo, requiring a gui_reset to recover. gui con?uration register name: guireg_cfg address: gbase | queued_reg | 00000030h, read/write address: gbase | non_queued_reg | 00000030h, read/write size: 32 bit function: the gui con?uration register controls the overall context of the gui accelerator determining such functions as pixel color depth for line or blt, raster operation to be used, etc. the contents of the gui con?ura- tion register are shown in table 107. at reset all bits are cleared except [18:16], as indicated. table 106. example bitmap context register allocation bit map # selector # typical allocation 0 000 mono pattern 1 001 color pattern 2 010 screen copy 3 011 spare 4 100 mono host ? 5 101 color host ? 6 110 solid fill ? 7 111 free ? ? reserved for host and solid ?l operations gui a ccelerator gui registers btv2115 brook t ree 177 bt table 107. gui con?uration register (guireg_cfg) (1 of 2) bit(s) description 31:23 reserved 22 read only status bit for gui ram bist (see grp_cfg6[0] table 20 on page 48) 1 = bist complete on gui result fifo rams 21 read only status bit for gui ram bist (see grp_cfg6[0] table 20 on page 48) 1 = control ram bist pass 0 = control ram bist fail 20 read only status bit for gui ram bist (see grp_cfg6[0] table 20 on page 48) 1 = data ram bist pass 0 = data ram bist fail 19 byte 3 write control 1 = preserve alpha channel 0 = modify alpha channel the byte 3 write control bit should only be set in 32bpp mode to pre- serve the ?lpha channel?data in byte 3 of 32-bit pixels. when set to 1, the bit disables byte enable 3 on all dwords the gui writes to vram. to ensure predictable results, be sure that the gui is idle and the result ?o is empty (guireg_depth[19:0] =0) before the byte 3 write control bit is toggled. 18:16 color depth 000= 1bpp (mono) reserved 001= 4bpp 010= 8bpp (reset value) 011= reserved 100= 16 bpp 101= reserved 110= 24 bpp 111= 32 bpp 15:14 reserved 13:12 transparency control 00= no transparency 01= source transparency 10= reserved 11= reserved gui a ccelerator gui registers btv2115 brook t ree 178 bt foreground color register name: gui_fg_color address: gbase | queued_reg | 00000020h, read/write address: gbase | non_queued_reg | 00000020h, read/write size: 32 bit function: in all modes where the color depth is less than 32 bits per pixel, color values must be replicated to ?l the foreground color register. for ex- ample, in 8bpp mode, the 8 bit color index to be used for foreground write operations must be replicated across all four bytes of the fore- ground register. in 24 bpp mode, byte3 must be set equal to byte0. the bit contents of the foreground color register are shown in table 108. 11:9 reserved 8 mono_flip_enable 0= pass monochrome bitmap bytes through unscathed. 1= reverse the bits within each byte in monochrome bitmaps before alignment. 7:5 reserved 4:0 rop code 00h= 01h= 02h= 03h= 04h= 05h= 06h= 07h= 08h= 09h= 0ah= 0bh= 0ch= 0dh= 0eh= 0fh= 10h:1fh s-->d s and d --> d s and d --> d 0 --> d s or d --> d s xnor d --> d d --> d s nor d --> d s or d --> d d --> d s xor d --> d s and d --> d 1 --> d s or d --> d s nand d ->d s --> d reserved source replaces dest and source with dest and source with not dest 0s replace dest or source with not dest xnor source with dest invert dest nor source with dest or source with dest no change xor source with dest and not source with dest 1s replace dest or not source with dest nand source with dest not source replaces dest table 108. foreground color register bit(s) description 31:0 foreground color table 107. gui con?uration register (guireg_cfg) (2 of 2) bit(s) description gui a ccelerator gui registers btv2115 brook t ree 179 bt background color register name: gui_bg_color address: gbase | queued_reg | 00000024h, read/write address: gbase | non_queued_reg | 00000024h, read/write size: 32 bit function: this value is used for writing pixels for solid ?ls or when in one of the patterned modes, and the pattern bit is a zero. if color depth is less than 32 bpp, then color values must replicated in the same manner as for the foreground register. the bit contents of the background color register are shown in table 109. destination xy increment register name: gui_dest_xy_inc address: gbase | queued_reg | 0000002ch, read/write address: gbase | non_queued_reg | 0000002ch, read/write size: 32 bit function: this value is used to increment the internal destination xy register af- ter the completion of a blt command, allowing a blt offset to be spec- i?d. the bit contents of the destination xy increment register are shown in table 110. blt control register (direction) name: gui_blt_control address: gbase | queued_reg | 00000034h, read/write address: gbase | non_queued_reg | 00000034h, read/write size: 32 bit function: if blt backwards is selected, the dst and src xy both point to the last pixel of the respective ?lds. also both x and y are decremented throughout the operation. the bit contents of the background color reg- ister are shown in table 111. table 109. background color register bit(s) description 31:0 background color value table 110. destination xy increment bit(s) description 31:28 y sign extended 27:16 signed y increment value 15:12 x sign extended 11:0 signed x increment value gui a ccelerator gui registers btv2115 brook t ree 180 bt line control register name: gui_line_control address: gbase | queued_reg | 00000038h, read/write address: gbase | non_queued_reg | 00000038h, read/write size: 32 bit function: the line control register de?es how several line drawing situations are handled. a single pixel line [(x0,y0)=(x1,y1)] with either skip _ first or skip _ last is effectively a no-op (bresenham regis- ters are modi?d but not frame buffer, nor is the line pattern stepped). the bit contents of the line control register are shown in table 112. table 111. blt control register bit(s) description 31:1 reserved 0 direction (1=backward), cleared after each operation. table 112. line control register (1 of 2) bits field description 31:11 unused 10 a. xmajor 1 = x axis is the major axis 0 = y axis is the major axis 9 a. sign_dx 1 = dx is negative 0 = dx is positive 8 a. sign_dy 1 = dy is negative 0 = dy is positive 7:6 unused 5 b. x_reversible 1 = draw line reversibly, x-windows style. when nt_reversible is set, it overrides x_reversible. 4 calc_only 1 = calculate all constants and addresses but don? draw 3 skip_first 1 = do not draw the ?st pixel on a line segment gui a ccelerator gui registers btv2115 brook t ree 181 bt zero-parameter line draws are not affected by calc _ only , allowing a se- quence of (1) draw _ line ( calc _ only ) (2) modify bresenham registers (3) draw _ line (no parameters). line pattern register name: gui_line_pattern address: gbase | queued_reg | 00000028h, read/write address: gbase | non_queued_reg | 00000028h, read/write size: 32 bit function: this register is used to control the style of lines drawn. when bit 0 is set to ?,?the current pixel is drawn in foreground color. when bit 0 is set to ?,?the current pixel is drawn in background color. the contents of the line pattern register are rotated one bit position to the right for every line pixel drawn; i.e., bits 31:1 become bits 30:0 and bit 0 be- comes bit 31. the line pattern register is not reset between line draw operations, so it will track through polyline operations. once the gui is enabled (grp_cfg4[0] = 1), the pattern is reinitialized only by writing to this pattern register. the contents of this register are ignored unless a source bitmap with the pattern bit is selected (see table 103, ?itmap register type field,?on page 175). 2 skip_last 1 = do not draw the last pixel on a line segment. 1 b. invert_zero_ test 1 = for zero-error-term cases, inverts the deci- sion to step in the major and minor or just major axis for nt_reversible, x_reversible, and non-reversible line draws 0 = not enable invert zero test 0 b. nt_reversible 1 = draw line reversibly, nt style. for nt lines always choose lower x or y value. when set, overrides x_reversible. 0 = disable nt style. if both nt_reversible and x_reversible are set to 0, non- reversible lines are drawn a. bits 10:8 control the effective drawing octant for zero-parameter lines. these bits are ignored and overwritten when the line draw engine calculates the breshen- ham parameters. b. if bits 0, 1, and 5 are set to ?,?the line engine will step both axes when the error term is zero. table 112. line control register (2 of 2) bits field description gui a ccelerator gui registers btv2115 brook t ree 182 bt bresenham 0, address register name: gui_bres0_addr address: gbase | queued_reg | 00000080h, read/write address: gbase | non_queued_reg | 00000080h, read/write size: 32 bit function: the value in this register is normally computed from the xy to linear address logic which converts incoming xy addresses to linear frame buffer addresses. the bit contents are shown in table 113. bresenham 0, error register name: gui_bres0_err address: gbase | queued_reg | 00000084h, read/write address: gbase | non_queued_reg | 00000084h, read/write size: 32 bit function: the value in this register is normally computed from the line command setup logic, unless a zero parameter line command was issued. the val- ue is also computed in the calc _ only mode of line draw. the value is set as required for the bresenham line draw algorithm. the bit contents are shown in table 114. bresenham 0, k1 register name: gui_bres0_k1 address: gbase | queued_reg | 00000088h, read/write address: gbase | non_queued_reg | 00000088h, read/write size: 32 bit function: the value in this register is normally computed from the line command setup logic, unless a zero parameter line command was issued. the val- ue is also computed in the calc _ only mode of line draw. the value is set as required for the bresenham line draw algorithm. the bit contents are shown in table 115. table 113. bresenham 0, address register bit(s) description 31:25 reserved, set to zero 24:5 dword address 4:2 nibble address for 4 bpp modes 1:0 reserved, set to zero note: 8bit address requires byte, 16bit address requires a word, 24bit address requires byte, 32bit address requires dword table 114. bresenham 0, error register bit(s) description 31:0 error value gui a ccelerator gui registers btv2115 brook t ree 183 bt bresenham 0, k2 register name: gui_bres0_k2 address: gbase | queued_reg | 0000008ch, read/write address: gbase | non_queued_reg | 0000008ch, read/write size: 32 bit function: the value in this register is normally computed from the line command setup logic, unless a zero parameter line command was issued. the val- ue is also computed in the calc _ only mode of line draw. the value is set as required for the bresenham line draw algorithm. the bit contents are shown in table 116. bresenham 0, increment 1 registers name: gui_bres0_inc1 address: gbase | queued_reg | 00000090h, read/write address: gbase | non_queued_reg | 00000090h, read/write size: 32 bit function: the value in this register is normally computed from the line command setup logic, unless a zero parameter line command was issued. the val- ue is also computed in the calc _ only mode of line draw. the value is set as required for the bresenham line draw algorithm. the bit contents are shown in table 117. bresenham 0, increment 2 registers name: gui_bres0_inc2 address: gbase | queued_reg | 00000094h, read/write address: gbase | non_queued_reg | 00000094h, read/write size: 32 bit function: the value in this register is normally computed from the line command setup logic, unless a zero parameter line command was issued. the val- ue is also computed in the calc _ only mode of line draw. the value is set as required for the bresenham line draw algorithm. the bit contents are shown in table 117. table 115. bresenham 0, constant k1 bit(s) description 31:0 k1 value table 116. bresenham 0, constant k2 bit(s) description 31:0 k2 value gui a ccelerator gui registers btv2115 brook t ree 184 bt bresenham 0, length register name: gui_bres0_length address: gbase | queued_reg | 00000098h, read/write address: gbase | non_queued_reg | 00000098h, read/write size: 32 bit function: the value in this register is normally computed from the line command setup logic, unless a zero parameter line command was issued. the val- ue is also computed in the calc _ only mode of line draw. the value is set as required for the bresenham line draw algorithm. the bit contents are shown in table 118. table 117. bresenham 0, increment 1 and 2 registers bit(s) description 31:18 sign extend bit[17] (writes bit 17 into this ?ld) 17:2 increment value 1:0 set to zero table 118. bresenham 0 length register bit(s) description 31:12 reserved, set to zero 11:0 line pixel count - 1, e.g. (1,1)->(3,3) yields a length register value of 2. brook t ree 185 bt s oftware e ncoded v ideo (sev) p layer introduction the btv2115 sev module is capable of supplying data to the btv2487 pacdac sev module from the vram serial port. this module is capable of operating in- dependently of system software for one or more frames but it has complicated re- quirements for the organization of its data in vram memory. this module has non-trivial requirements for vram to btv2487 bandwidth that vary based on the compression achieved in the run length encoding and sev- eral other factors. if the necessary bandwidth is not available the sev fifo in the btv2487 will under?w. organization of display data in memory the display data is organized in vram memory in a linked list data structure, as shown in figure 20. s oftware e ncoded v ideo (sev) p layer introduction btv2115 brook t ree 186 bt a page table consisting of 32 bit dwords contains a pointer to the start of a data block and a count specifying the length of the display block. table 119 shows the bit de?itions of the page table entry. the data_cnt ?ld of the page table entry speci?s the length of the block of display data in memory. the length is speci?d in dwords; the length in bytes is 4 times this value. figure 20. organization of display data table 119. page table entry bits field name description 31:18 data_cnt number of dwords to transfer for this page table entry 17:0 data_ptr pointer to starting location in vram [21:4] field 1st odd odd vert. blanking field 1st even even vert. blanking 2nd even field 2nd odd field display data page table base__addr page_ptr vram btv2115 registers [21:2] copy . . . advances thru page table vram s oftware e ncoded v ideo (sev) p layer introduction btv2115 brook t ree 187 bt the data_ptr ?ld of the page table entry points to the start of a block of display data in memory. the data_ptr ?ld is 18 bits wide; these bits go to form a22-a4 which together with assumed values of 0 for a3-a0 allow the data block to begin at any 4 dword / 16 byte address in vram. note that is not possible to point to any data block in memory at anything other than a 4 dword / 16 byte ad- dress (i.e. anything with address bits a3-a0 non-zero). note that these restrictions on the starting address and length of the display data block in memory ensure that the display data block ends on a dword boundary. the restrictions on starting and stopping addresses for the display data in vram are essential because the btv2115 is unable to transfer anything other than dwords over the vram serial port. without these restrictions this module would be im- possible to implement - however these restrictions impose some requirements on the programmer when generating the display data. the simplest way that these re- quirements could be satis?d is if the programmer adjusts some repeat blocks within the run length data to ensure that each block of display data is a multiple of 4 bytes in length - this will ensure that no sev repeat data structure spans over more than one display data block in memory. if this is not possible then the pro- grammer must ensure that the data in the second and subsequent display data block is set up to remain in sync with the run-length encoded data coming from the pre- vious block. a value of 0 in the page table entry data_cnt ?ld signi?s the end of the page table. when the sev module gets to this entry in the page table it ignores the pointer part of the entry, goes back to the start of the page table and begins pro- cessing from there again. there is no limitation on the smallest repeat count allowable in the data_cnt ?ld of a page table entry, however because each page table entry initiates at least one vram serial transfer to the btv2487 a long sequence of very small display data blocks will likely lead to the btv2487 sev block running out of data. the actual minimum value will depend on various other issues like how much bandwidth is made available on the vram serial port for the transmission of sev data, how compressed the sev data is, etc. it is the responsibility of the programmer to ensure that suf?ient vram serial port bandwidth is available and that it is used ef?iently enough to ensure that the btv2487 sev module does not run out of data. limitations on the display data the limitations on the display table are listed below. all page table and display data must be in the vram. the start of the page table can be anywhere in vram - i.e. it must be at an address with an a1-a0 of zero. the page table can be any length and is limited only by the size of vram. the end of the page table is indicated by a page table entry with a count value of 0. each block of display data must begin on a 16 byte or 4 dword boundary. (i.e. a vram address where a3-a0 are zero.) s oftware e ncoded v ideo (sev) p layer introduction btv2115 brook t ree 188 bt each block of the display data must end on a dword boundary. (i.e. a vram address where a1-a0 are zero.) the maximum length of a block of display data is 2 14 dwords, or 64kb. it is possible to make up a longer block of display data by stringing to- gether two or more page table entries. s oftware e ncoded v ideo (sev) p layer programming the sev block btv2115 brook t ree 189 bt programming the sev block the vast majority of the programming involved with the btv2115 sev block is in setting up the display data and page tables in vram memory. once all the data is set up the programmer can start the sev module by writing the sev grp_sv_ctrlw register and observing the operation of the sev module by reading the sev grp_sv_ctrlr register. sev controller write register name: grp_sv_ctrlw[3:0] index: b4h:b1h, write only size: 32 bit function: this is a graphics extension register used to control the operation of the soft video module. the contents of the bit registers are shown in table 120. the bits are further explained in the paragraphs that follow. grp_sv_ctrlw[31] (enable) the enable bit enables/disables the operation of the btv2115 sev module. currently the enable bit prevents the sev module from operating - if the en- able bit is de-asserted while the sev module is already operating it will be in- terpreted as a reset and the sev module will drop what it is doing and stop generating sev data for the btv2487. the reset condition of the enable bit is de-asserted. table 120. sev grp_sv_ctrlw register bits field name description 31 enable 1 = enable sev operation 0 = reset sev module 30 ptop 1 = pause at top of list 0 = normal operations 29 pimm 1 = pause immediately upon setting this bit 0 = normal operation 28:24 unused 23:22 pkt_size 00 = 32 dword packets 01 = 64 dword packets 10 = 128 dword packets 11 = 256 dword packets 21:2 base_addr pointer to ?st page table entry in vram. 1:0 reserved set to zero s oftware e ncoded v ideo (sev) p layer programming the sev block btv2115 brook t ree 190 bt grp_sv_ctrlw[30] (ptop) the ptop (pause at top) bit pauses the sev module when it gets to the top of the page table. this is useful for when the programmer is writing to the grp_sv_ctrlw register. if this bit is asserted, the sev module pauses just be- fore copying the base_addr ?ld to the page_ptr register. this is useful because the access to the base_addr ?ld is split over 3 8-bit writes and it could be hazardous to allow the possibility of the base_addr ?ld being trans- ferred to the page_ptr register while it is partially updated. grp_sv_ctrlw[29] (pimm) the pimm (pause immediately) bit is similar to the ptop bit in that it stops the sev module just after it s next transfer of video data to the btv2487 but before it updates the page_ptr, data_prt or data_cnt registers. with the current implementation of the sev module the programmer must wait for at least one cy- cle after the sev module sees the pimm bit asserted before reading the page_ptr or data_cnt ?lds of the grp_sv_ctrlr register. the sev module is guaranteed to have gotten at least as far through the video data as indi- cated by the values read from the grp_sv_ctrlr register. the sev module may have proceeded further by as much as a vram packet - however due to the way this module is designed there is no way for the programmer to determine if this is so. setting either the ptop or pimm bit for any appreciable period of time could cause erroneous behavior in the sev module and waste vram to btv2487 band- width causing the btv2487 sev module to run out of video data to display. the programmer should only assert either of these bits for a short time. assert the ptop bit just before writing to the grp_sv_ctrlw register base_addr field, and assert the pimm bit just before reading the grp_sv_ctrlr register data_cnt or page_ptr ?lds. immediately deassert the relevant bit when ?ished. the enable, ptop, and pimm bits are in a separate byte all by themselves so that it is easy to write to them without upsetting any of the other ?lds. grp_sv_ctrlw[23:22] (pkt_size) the pkt_size ?ld is a 2 bit ?ld that controls the maximum size of serial packet to use in transferring data. the available packet sizes are shown in table 121. the reset value of the pkt_size ?ld is not de?ed. table 121. packet size used pkt_size bytes/packet dword cycles/packet 2?00 128 32 2?01 256 64 2?10 512 128 2?11 1024 256 s oftware e ncoded v ideo (sev) p layer programming the sev block btv2115 brook t ree 191 bt grp_sv_ctrlw[21:2] (base_addr) the base_addr f ield is 20 bits wide and indicates the start address for the page table in vram memory. this ?ld is copied to the page_ptr register when enable is ?st asserted and again whenever the sev module reaches the end of the page table in memory. this is a 20 bit dword address into the 4m address space of the vram. the reset value of the base_addr f ield is not de?ed. sev controller read register name: grp_sv_ctrlr[3:0] index: b4h:b1h, read only size: 32 bit function: this is a graphics extension register used to control the read operation of the soft video. the grp_sv_ctrlr register allows you to check the status of the btv2115 sev module. both the data_cnt and page_ptr ?lds are the contents of internal registers within the sev module. the contents of the bit registers are shown in table 122. the bits are further explained in the paragraphs that follow. grp_sv_ctrlr[31:18] (data_cnt) the data_cnt register contains the number of dwords of data remaining to be transferred in the current display data block. whenever the sev module moves to a new page table entry, this register is loaded from the data_cnt ?ld of the page table entry. as packets of data are transferred over the vram serial bus to the btv2487, this register is decremented to keep track of the number of dwords remaining to be transferred. the data_cnt register is decremented by the ap- propriate packet size (as de?ed by the pkt_size ?ld, see table 120 on page 189) whenever video data is sent to the btv2487 from the vram serial port. if the value is not a integral number of packets, then everything proceeds as before except that the fractional part of a packet is transferred as a smaller last packet. thus, the location of the sev module within the display frame is determined. the page_ptr ?ld contains the currently processed display data block. the data_cnt speci?s where in that data block the processing currently is. table 122. sev grp_sv_ctrlr register bits field name description 31:18 data_cnt number of dwords yet to be transferred in the currently active page_table entry 17:0 page_ptr address of the page_table entry that is cur- rently being processed. s oftware e ncoded v ideo (sev) p layer programming the sev block btv2115 brook t ree 192 bt grp_sv_ctrlr[15:0] (page_ptr) the page_ptr register points to the current page table entry (on a dword ad- dress). initially after the enable bit in the grp_sv_ctrlw register is ?st as- serted, this register is copied from the base_addr ?ld in the grp_sv_ctrlw register to point at the ?st entry in the page table in memory. as the sev module moves through the page table, this register is also incremented and can be read to see how far through the page table the btv2115 sev module has advanced. note that the base_addr ?ld in the grp_sv_ctrlw register is 22 bits wide and the page_ptr ?ld in the grp_sv_ctrlr register is only 18 bits. the missing bits are two msbs and two lsbs. these bits are ignored in the base_addr ?ld because only dword accesses are available from the vram. s oftware e ncoded v ideo (sev) p layer accessing sev registers btv2115 brook t ree 193 bt accessing sev registers the access mechanism to the grp_sv_ctrlr and grp_sv_ctrlw regis- ters is via the vga graphics extension bus. the grp_sv_ctrlw and grp_sv_ctrlr registers are mapped to the same addresses on the vga graph- ics extension bus. since grp_sv_ctrlw is write only and grp_sv_ctrlr is read only, they can share addresses with no problems. the soft video registers are 32 bits wide and the vga graphics extension bus is 8 bits wide. this difference in register length could lead to problems because one read/write could be broken into separate 8-bit read/writes. to prevent the acciden- tal read/write of incorrect data, access to each of these registers is divided into four separate 8-bit reads/writes, as shown in figure 21. when reading the grp_sv_ctrlr register, both the data_cnt (grp_sv_ctrlr[31:18]) and page_ptr (grp_sv_ctrlr[17:0]) ?lds could be changing while the soft video is running. these ?lds require two or more 8-bit reads, which could result in an incorrect result if the value of these ?lds change between the 8-bit reads. if the software driver does not need to access the full contents of these ?lds (for example, one page table is smaller than 256 en- tries), then the software could read only, for example, the least signi?ant byte of grp_sv_ctrlr to determine where in the page table the soft video module is currently processing. if full accuracy is required, a possible solution is to pause the soft video module while the full contents of the grp_sv_ctrlr register is read. to do this, assert the pimm bit of the grp_sv_ctrlw register, then write the pimm bit again to allow the soft video module to continue. this procedure will figure 21. accessing sev registers through vga extension bus 7 8 15 16 23 24 31 7 8 15 16 23 24 31 ctrlw ctrlr grp_sv_ x [3] grp_sv_ x [2] grp_sv_ x [1] grp_sv_ x [0] 50h 51h 52h 53h 0 0 s oftware e ncoded v ideo (sev) p layer accessing sev registers btv2115 brook t ree 194 bt cause the soft video module to pause immediately; in an extreme case this could cause the video fifo in the pacdac to under?w. when writing to the grp_sv_ctrlw register, the base_addr ?ld (grp_sv_ctrlw[21:2]) must be broken into three separate 8-bit writes. it is possible that the soft video module will reach the end of its vram page_table and attempt to reload the page_ptr register from a base_addr ?ld which is only partially updated. to avoid this problem, write the most-signi?ant byte of this register to set the ptop bit. this action will pause the soft video module if it reaches the top of the vram page_table, thus preventing the use of an incom- plete base_addr. when the three low order bytes are written to the grp_sv_ctrlw register, the most signi?ant byte can be written again to clear the ptop bit. this procedure pauses the soft video module only when it reaches the end of its vram page_table and is ready to return to the top. brook t ree 195 bt pacdac c ontroller introduction the pacdac controller of the btv2115 is essentially a state machine capable of interpreting a vram resident data structure. this data structure is a compacted representation of the display environment which determines system parameters such as pixel width, screen resolution, size and position of video windows, cursor location, serial clock and pixel clock rates, etc. in short the data structure stores all information necessary to completely de?e the entire display state. the pacdac controller is responsible for processing this data structure and clocking the perti- nent elements from vram to the btv2487. this chapter describes btv2115 func- tional support of these features, the format of the data structure and its usage. the btv2115 registers used to control the pacdac are de?ed in the ?egis- ter de?itions?starting on page 55. for more information on the pacdac, refer to the btv2487 pacdac speci? cation . pacdac c ontroller pacdac data types btv2115 brook t ree 196 bt pacdac data types data is transferred by the pacdac controller from vram to the btv2487 pac- dac via the vram serial port. blocks of data are tagged using the pt[3:0] pins of the btv2115 to indicate to the btv2487 pacdac the type of data currently at the inputs of the pacdac. table 123 shows the data type assignments for the pt[3:0] pins. the pt and serial data from the vram are synchronous to lclk[1:0]. each lclk rising edge clocks a full 32 bit dword into pacdac. pt types are never mixed within a dword. the rst pt data type is used to reset the btv2487 pacdac without perform- ing a system reset. setting grp_cfg5[6] (see table 21 on page 49) will cause the pacdac controller to warm reset the btv2487 pacdac by issuing rst pt data types until bit 6 is cleared. vram serial data coincident with the dr pt data type contains either a regis- ter address or register data to be written into the register ?e of the btv2487 pac- dac. the ts pt data type indicates information which is used by the btv2487 pac- dac to determine when to begin loading or unloading its internal fifo set, the correct assertion of crt control signals such as hsync and blank, and the timing for the lsync handshake signal. the noop pt data type is used to initialize the vram serial register between packet types. table 123. pt[3:0] data type assignments address data type description 0h reserved 1h cd cursor pixels 2h gd graphics pixels 3h v1 video fifo 1 pixels 4h v2 video fifo 2 pixels 5h dr btv2487 (dac) register data 6h ts timing structure data 7h - dh reserved eh noop no operation fh rst reset pacdac c ontroller master structure btv2115 brook t ree 197 bt master structure the core of the pacdac controller data structure is the master structure. the el- ements within the master structure s sequentially accessed list contain either di- rect information or pointers to substructures that de?e aspects of the display state. the master structure is processed at the top of each frame allowing screen format changes at the frame rate. the btv2115 supports two master structures to allows alterations to the inac- tive master structure and substructures without effecting the current display state. the dual structures and the associated master structure switching mechanism per- mit graceful mode switching between screen formats. the dual master structure pointers, labeled a and b, are accessed via the i/o registers pdc_msptra and pdc_msptrb (de?ed in ?aster structure a ad- dress register?on page 55 and ?aster structure b address register?on page 56). the switching mechanism is accessed via the pdc_cntl register (see page 57). pdc_msptra and pdc_msptrb contain byte addresses which point to the ?st dword of the respective master structure. bits [1:0] of pdc_msptra and pdc_msptrb always contain zeroes. the pacdac controller also uses the dac register structure, which contains the desired register state for the btv2487 pacdac during the ensuing frame and the timing structure, which contains information describing the screen formatting used during the ensuing frame. table 124 de?es the contents of the master structure. details on the different data types are provided following the table. an example of a master structure set- up is provided at the end of this chapter. pacdac c ontroller master structure btv2115 brook t ree 198 bt table 124. master structure entry format (1 of 3) entry name field bits description graphics data pkt_ordr 31:00 packet ordering control gd_pntr 31:20 reserved pntr 19:00 dword pointer to start of graphics data gd_y 31:28 reserved y_end 27:16 screen row ending position + 1 15:12 reserved y_strt 11:00 screen row starting position gd_x ptch 31:16 pitch of graphics data 15:12 reserved x_cnt 11:00 number of dwords to send to pacdac per screen row cursor data cd_pntr 31:20 reserved pntr 19:00 pointer to start of cursor data cd_y 31:28 reserved y_end 27:16 screen row ending position + 1 15:12 reserved y_strt 11:00 screen row starting position cd_x ptch 31:16 pitch of cursor data 15:12 reserved x_cnt 11:00 number of dwords to send to pacdac per screen row pacdac c ontroller master structure btv2115 brook t ree 199 bt video 1 v1_pntra 31:20 reserved pntr 19:00 pointer to video 1 data, 1 of 2 v1_pntrb 31:20 reserved pntr 19:00 pointer to video 1 data, 2 of 2 v1_y 31:28 reserved y_end 27:16 ending row position + 1 15:12 reserved y_strt 11:00 starting row position v1_x ptch 31:16 pitch of video 1 data 15:12 reserved x_cnt 11:00 number of dwords to send to pacdac per screen row v1_yscl 31:15 reserved rsvd 14:13 reserved (write zeroes) y_sinc 12:00 y scale increment, video 1 ( i .ffffffffffff) video 2 v2_pntra 31:20 reserved pntr 19:00 pointer to video 2 data, 1 of 2 v2_pntrb 31:20 reserved pntr 19:00 pointer to video 2 data, 2 of 2 v2_y 31:28 reserved y_end 27:16 ending row position + 1 15:12 reserved y_strt 11:00 starting row position v2_x ptch 31:16 pitch of video 2 data 15:12 reserved x_cnt 11:00 number of dwords to send to pacdac per screen row v2_yscl 31:15 reserved up_mode 14:13 see table 125 on page 202 y_sinc 12:00 y scale increment, video 2 ( i .ffffffffffff) table 124. master structure entry format (2 of 3) entry name field bits description pacdac c ontroller master structure btv2115 brook t ree 200 bt packet ordering the order by which pt data types (also called packet types) are sent to the btv2487 pacdac is controllable via the pkt_ordr master structure entry. each nibble of pkt_ordr de?es a pt data type. the sequence is processed from ls nibble to ms nibble; all six nibbles are processed during each scan line with the same packet order used for each. all pt data types shown in table 123 are valid, except the rst pt data type which is generated in hardware within the pacdac controller. each nibble entry in pkt_ordr must be unique except the noop which may be added as neces- sary to pad out the pkt_ordr entry. for example, a typical pkt_ordr entry could be 124356h, which would cause the pacdac controller to send pt data types in this sequence: ts, dr, v1, v2, gd, cd. a system which did not require video or cursor functions might use the following pkt_ordr entry, ee2e56h. pkt_ordr determines only the ordering of pt data type. the pacdac con- troller determines whether a given pt data type is needed for a given scan line and sends only those which are required to format the scan line. graphics data the master structure ?ld gd_pntr.pntr points to the location of the ?st dword of graphics data within the frame buffer. this entry is a twenty bit dword ad- dress. gd_y contains values which de?e the vertical boundaries for displayed graphics pixels. screen position values are based on an arbitrary reference point usually line 0. typically line 0 will be the ?st scan line of the vsync period. the timing structure data ts_pntr 31:20 reserved pntr 19:00 pointer to timing structure ts_leng 31:20 reserved leng 19:00 sum of all nats ?lds (refer to table 127) in the timing structure dac register data dr_pntr 31:20 reserved pntr 19:00 pointer to dac registers dr_end 31:28 reserved blk 27:20 register transfer block size end 19:00 end of dac register clock data misc 31:28 reserved nxt_line 27:16 initial next line value clk_mod 15:00 [15:4] graphics clock modulation [3:00] io clock modulation table 124. master structure entry format (3 of 3) entry name field bits description pacdac c ontroller master structure btv2115 brook t ree 201 bt starting screen row, line 0 in this example, can be programmed using the nxt_line ?ld of the misc master structure entry. gd_y.y_end contains the position of the last screen row of displayed graphics pixels+ 1. gd_y.y_strt contains the screen row of the ?st line of displayed graphics pixels. gd_x contains values which constrain the horizontal boundaries for graphics data in units measured in dwords. gd_x.ptch is the graphics data pitch. pitch is de?ed as the difference between the addresses of two vertically adjacent pixels, in dwords. gd_x.x_cnt speci?s the number of dwords contained in a single line of graphics data. commonly ptch and x_cnt will contain the same value if graphics data is packed without gaps between the last pixel of line n and the ?st pixel of line n+1. to determine the correct value for x_cnt multiply the number of bits per pixel times the number of horizontal pixels and divide the quantity by 32. the majority of the remaining data types shares a common format with that ex- plained above. cursor data the master structure ?ld cd_pntr.pntr points to the starting location of the cursor data register. this entry is a twenty bit dword address. cd_y.y_strt contains the value of the ?st line of the cursor. cd_y.y_end contains the last line of the cursor + 1. cd_x.ptch contains the pitch of vertically adjacent cursor pixels as stored in the frame buffer. cd_x.x_cnt contains the number of dwords in a single row of cursor data. video data the pacdac controller supports two double buffered video windows. the win- dows are labeled 1 and 2 and the dual buffers for each are labeled a and b. the master structure ?lds v1_pntra.pntr, v1_pntrb.pntr, v2_pntra.pn- tr, and v2_pntrb.pntr point to the starting location of the data for video win- dow 1a and 1b and video window 2a and 2b, respectively. the formatting for buffers a and b are exactly the same, they share ptch, y_sinc, etc. the dual buffering mechanism allows removal of artifacts caused by the asynchronous vid- eo capture and display scan rates common in other systems. the v1_pntra.pntr, v1_pntrb.pntr, v2_pntra.pntr, and v2_pntrb.pntr master structure entries are twenty bit dword addresses. upscaling in x and y is supported in the btv system; the pacdac performs virtually all upscaling along the x axis. pacdac controller support is required for upscaling in the y direction. the heart of this mechanism is a 12+1 bit dda that determines which lines of screen data to send to the pacdac. two types of upscaling are available in the pacdac. interpolated upscaling analyzes two pixel values to determine which value to display. replicated upscal- ing displays a single pixel value multiple times. interpolation results in a higher quality image, however only a single interpolated window is supported within the btv architecture. in replicated mode, two independent upscaled windows are pos- sible. pacdac c ontroller master structure btv2115 brook t ree 202 bt the master structure supports up to four different video buffers: v1_pntra, v1_pntrb, v2_pntra, and v2_pntrb. in a con?uration which does not re- quire upscaling or uses replicated upscaling the use of the four pointers is straight forward, v1_pntra and v1_pntrb control the display and capture buffers for video window 1. likewise, v2_pntra and v2_pntrb control the display and capture buffers for video window 2. in interpolated con?urations these pointers have slightly different usages. the upscaling mode is de?ed in the ?ld up_mode within the v2_yscl master structure entry, bits v2_yscl[14:13]. ( v2 is considered the primary win- dow.) v1_yscl[14:13] is reserved for future architectures and should be written with 0x0.) the up_mode values specify how to increment the video pointers. table 125 shows the up_mode bit de?itions and the number of windows supported; addi- tional information follows the table. the replication upscaling is performed based on y_sinc. the dda adds the y_sinc value to the accumulator and checks for over?w. if over?w occurs the video pitch is added to both a and b pointers. if over?w does not occur the point- ers are unchanged. the y_sinc ?ld contains a 13 bit ?ld de?ed as: i.ffffffffffff the decimal point is located to the right of the msb. setting the ms bit to a 1 forces an over?w on the 12 bit accumulator value, essentially disabling the dda table 125. up_mode bit de?itions bit defs. function windows description 00 no upscaling 1 or 2 increment both a and b pointers for a given window after sending a line of video. incrementing is accomplished by adding the pitch value for the window to both pointers. pointers a and b for each window move in lock step. 01 upscale with replication 1 or 2 increment both a and b pointers for a given window after sending a line of video. incrementing is accomplished by adding the pitch value for the window to both pointers only if a dda over?w occurs when y_sinc is added. 10 upscale with interpola- tion 1 pointers v1_pntra, v1_pntrb, v2_pntra, and v2_pntrb are altered. two pointers are required for each buffer. see explanation below. 11 reserved pacdac c ontroller master structure btv2115 brook t ree 203 bt and causing the pacdac controller to increment the pointers by the pitch value each time. interpolation upscaling alters the pointers v1_pntra, v1_pntrb, v2_pntra, and v2_pntrb. two pointers are required for each buffer. a pair of pointers are used to indicate line n and line n+1 within each video buffer. during one line of displayed video, both line n and line n+1 are transmitted to the pac- dac from the active buffer. the pacdac uses its internal interpolator to process pixels from m and m+1 and determine the resulting pixel for display. interpolation upscaling supports beam crossing, but only one window is displayable. for interpolated upscaling the convention is that v1_pntra points to line n of the a buffer and v2_pntra points to line n+1 of the a buffer, similarly for the b buffer. once both lines are sent for the active buffer, the pacdac controller uses the dda to determine whether to increment the pointer values. the increment value v2 y_sinc is used for calculations in this mode, v1 y_sinc is extraneous. y_sinc is added to the accumulator value. if an over?w occurs, v2_pntra is copied to v1_pntra and v2_pntrb is copied to v1_pntrb. v2_pntra and v2_pntrb are then incremented by v1_x ptch. v1_x ptch is not used in this con?uration. the buffer pointer pairs increment in lock step. in this con?ura- tion, video fifo unload commands for fifo 1 and 2 must be simultaneous in the timing structure. beam crossing (or frame rate conversion) deals with removing visible artifacts from live video, especially scenes which contain motion. these artifacts are a re- sult of the differing frame rates of the sampled captured video and the display sys- tem. video sources tend to have a lower frame rate than high resolution graphics display systems. the result is that at some point a single frame of displayed video will have data from the previous frame and data from the current frame on the dis- play at the same time. for still images this is not as visible. however, since the eye is very sensitive to motion, live images which contain a high degree of motion will show undesirable artifacts. the solution to this problem is the use of two buffers for each video window: one for display and one for capture. at appropriate times, the pointers to these buffers are switched, removing motion artifacts. this switch control is accomplished outside of the pacdac controller in the video data struc- tures. v1_pntr.pntr is a twenty bit dword address pointing to the ?st valid data in the video window 1 a buffer. v1_pntrb.pntr is a pointer to the ?st valid data in the video window 1 b buffer. v1_y.y_end indicates the ending row position + 1 of video window 1. v1_y.y_strt indicates the starting screen row position for window 1. buffers a and b use the same y_end and y_strt values. v1_x.ptch signi?s the video window 1 pitch for vertically adjacent pixels of buffers a and b, as stored in the frame buffer. v1_x.x_cnt contains the number of dwords which must be sent to pacdac during active video lines for each row of video window 1. v1_yscl.y_sinc is a 12+1 bit quantity which is used in upscaling. y_sinc is the value which is added to the accumulator after each video line is sent, if the accumulator over?ws then v1_x.ptch is added to v1_pntr.pntr and stored pacdac c ontroller master structure btv2115 brook t ree 204 bt in v1_pntr.pntr. if the accumulator does not over?w the accumulator value is retained for the next line. the format of y_sinc is i.f. f is the 12 bit fractional value, i is the integer value. if i is set to a one the accumulator over?ws on each calculation, ptch is added to pntr, essentially disabling the dda. v2_pntr.pntr is a twenty bit dword address pointing to the ?st valid data in the video window 2 a buffer. v2_pntrb.pntr is a pointer to the ?st valid data in the video window 2 b buffer. v2_y.y_end indicates the ending row position + 1 of video window 2. v2_y.y_strt indicates the starting screen row position for window 2. buffers a and b use the same y_end and y_strt values. v2_x.ptch signi?s the video window 2 pitch for vertically adjacent pixels of buffers a and b, as stored in the frame buffer. v2_x.x_cnt contains the number of dwords which must be sent to pacdac during active video lines for each row of video window 2. v2_yscl.y_sinc is a 12+1 bit quantity which is used in upscaling. its usage is similar to that described for v1_yscl.y_sinc. v2_yscl.up_mode is used by both video window 1 and video window 2 to indicate the upscale mode required. table 125 summarizes the usage of this ?ld. timing structure data the timing structure is a sub-element which is linked to the master structure via the ts_pntr.pntr entry. its purpose is to format the display and provide control signals which inform the pacdac when to begin unloading its internal fifos or when to assert hsync, etc. the mechanism for this is described below. ts_leng.sum_nats indicates the total number of timing atoms in the tim- ing structure. the correct value for sum_nats is obtained by adding the nats ?lds of every ts_cnt entry in the timing structure. the discussion below de- scribes timing atoms and their format. timing atom the smallest element of the timing structure is called a timing atom. the timing atom contains a 12 bit run length and a 16 bit control state. the control state indi- cates the values which are to be assigned to various signals within pacdac. the 12 bit run length (horizontal repeat count, x_rep) indicates the number of pixel clocks to hold this control state. a separate atom is required for each change in the control state. therefore, each atom de?es a speci? timing region within a screen line. all pacdac signals will have the same value within a region, therefore tim- ing atoms run length encode the assertion of the control state in the horizontal di- rection. table 126 de?es the timing atom bits. pacdac c ontroller master structure btv2115 brook t ree 205 bt timing structure format the timing structure describes the position of the timing regions within a single frame by referencing timing atoms and formatting their presentation to pacdac. while the timing atom is responsible for horizontal run length encoding of the con- trol state, the timing structure in essence run length encodes the control state in the vertical direction. the timing structure is divided into sets of values, ?st a single entry which de- scribes the atom set, called ts_cnt, followed by a varying number of timing at- oms. this sequence is repeated as required to describe the display state for the frame. ts_cnt contains a ?ld labeled nats, which determines the number of tim- ing atoms in this set. ts_cnt also incorporates a ?ld labeled y_rep, which in- dicates the valid number of screen lines. the one bit ?ld fr_sync is used to indicate the top of frame for use in other sections of the btv2115. table 127 illustrates the timing structure format. table 126. timing atom bit de?itions bit item description detail 31 ls linesync 1= ready for new data 0= not ready 30 hs hsync out 1= drive hsync high 0= drive hsync low 29 vs vsync out 1= drive vsync high 0= drive vsync low 28 u1 unload video 1 1 = read from video fifo #1 0 = ignore video fifo #1 27 u2 unload video 2 1 = read from video fifo #2 0 = ignore video fifo #2 26 ug unload graphics 1 = read from graphics fifo 25 bl composite blank 0= display blanked 1= display not blanked 24 sy composite sync 1= sync not active 0= sync active (sync on green modes only) 23:18 reserved 17 co cursor origin 1= enable cursor x counter 0= disable cursor x counter 16 ga graphics signature 1= enable signature capture 0 = disable signature capture 15:12 reserved 11:0 ac atom count repeat count for timing atom pacdac c ontroller master structure btv2115 brook t ree 206 bt dac data the dac register structure holds the complete register state for the pacdac. the pacdac has an internal auto-incrementing address register, which requires only a starting address when programing a contiguous block of registers. the ?st entry in the dac register structure will contain a register index value. the pac- dac recognizes this as an address when it detects a 1 in bit 31 of the dword. then, when this dword is transferred to the pacdac by the pacdac controller, bit 31 causes the pacdac to load bits [9:0] into the auto-incrementing address register. thereafter, dwords which are sent with the dr pt data type are loaded into the register array as long as bit 31 of each dword is cleared. the pacdac address register post increments following register data writes. addresses may be mixed with register data as required to load a subset of the total pacdac register set. each register data entry in the dac register structure occupies a full dword one for each register. dr_pntr.pntr (a twenty bit dword address) points to the ?st entry in the dac register structure. dr_end.blk determines the number of dac register structure entries which are sent per line. sending the full complement of pacdac registers in a single line would typically over?w the pacdac internal dac register fifo, therefore a mechanism is provided to break the register set into blocks of size blk. dr_end.end is the twenty bit dword address of the last entry in the dac register structure. table 127. timing structure format name field bits description ts_cnt fr_sync 31 frame start ?g disp_active 30 active video is being displayed nats 29:16 number of atoms in set y_rep 15:00 vertical repeat count ts_atom ? c_st 31:16 control state 15:12 reserved x_rep 11:00 horizontal repeat count ts_atom ? c_st 31:16 control state, repeat 15:12 reserved x_rep 11:00 horizontal repeat count, repeat ? ts_atom is repeated as needed to describe a horizontal line. ts_cnt and ts_atom(s) are repeated as needed to describe a full frame. pacdac c ontroller master structure btv2115 brook t ree 207 bt the total number of entries in the dac register structure (dr_end - dr_pntr + 1) must be an integer multiple of dr_blk. this can be accom- plished by padding the dac register structure with the dr_index, followed by the appropriate number of palette entries or alternatively simply padding the end of the structure with multiple writes to the address register. pacdac c ontroller sample master structure setup btv2115 brook t ree 208 bt sample master structure setup this section provides a snippet of c code for setting up a generic master structure in vram and a dac register structure. as a minimum, at least these two struc- tures need to be initialized via software before the pacdac controller is enabled. for this example, the master structure b pointer registers are used. the same methodology can easily be used to initialize another structure in vram for master structure a. this example writes vram through the protected mode aperture, however the real mode aperture could have also been used. when the vga is enabled, it automatically generates the timing structure based on the values written to the vga registers at the address in vram pointed to by the master structure table entry ts_pntr. the length is calculated and the value is placed in the ts_leng entry. the vga also writes the dac register structure based on the address contained in dr_pntr and dr_end. for the graphics structure, the vga calculates the values for gd_x and gd_y and updates the ta- ble accordingly. if the vga is not enabled, then software is responsible for writing and maintaining all of these structures. //begin example //setup structure b pointer outp(grp_index,pdc_msptrb_0); //vram address 0x0ffa00(1 meg) outp(grp_data,0x00); outp(grp_index,pdc_msptrb_1); outp(grp_data,0xfa); outp(grp_index,pdc_msptrb_2); outp(grp_data,0x0f); //initialize master structure b in vram/ //first, packet order-->timing,dac regs,graphics memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x0,0x00000256l); //graphics data structure pointers memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x4,0x80000 >> 2);//gd_pntr memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x8,0); //gd_y memwr_dword(gbase | mba_direct | 0x000ffa00l | 0xc,0); //gd_x //cursor data structure pointers memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x10,0); //cd_pntr memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x14,0); //cd_y memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x18,0); //cd_x //display video 1 structure pointers memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x1c,0); //v1 ptr a memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x20,0); //v1 ptr b memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x24,0); //v1_y memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x28,0); //v1_x memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x2c,0); //v1_yscl pacdac c ontroller sample master structure setup btv2115 brook t ree 209 bt //display video 2 structure pointers memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x30,0); //v2 ptr a memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x34,0); //v2 ptr b memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x38,0); //v2_y memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x3c,0); //v2_x memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x40,0); //v2_yscl //timing structure pointers memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x44,0xff600 >> 2);//ts_pntr memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x48,0); //ts_leng //dac register structure pointers, pointer address - 1 dword memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x4c,0xfeffc >> 2); //dr_pntr //size of dac register table =300 dwords,block size=64 memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x50,0x6400000 | ((0xfeffc >> 2) + 300 -1)); / /dr_end //clock modulation for graphics and i/o packets memwr_dword(gbase | mba_direct | 0x000ffa00l | 0x54,0xc00c); //clk_mod //begin dac structure setup outp(grp_index,grp_pdac_0); //setup dac structure pointer outp(grp_data,0xfe); //vram address 0xff000, load bits 21:11, this is lsb outp(grp_index,grp_pdac_1); outp(grp_data,1); //msb of bits 21:11 outp(grp_index,grp_25pll_0); //setup pll register values outp(grp_data,0xa9); //25mhz setup outp(grp_index,grp_25pll_1); // outp(grp_data,0x0a); // outp(grp_index,grp_25pll_2); // outp(grp_data,0x00); // outp(grp_index,grp_28pll_0); //28mhz setup outp(grp_data,0x7c); // outp(grp_index,grp_28pll_1); // outp(grp_data,0x0b); // outp(grp_index,grp_28pll_2); // outp(grp_data,0x00); // //first dac pallet address word, for pdac regs 0x100-0x1ff,see btv2487 spec for details //dr_pntr points here memwr_dword(gbase | mba_direct | 0x000feffcl,0x80000100l); //dac register structure, for pdac regs 0-0xff,see btv2487 spec for details memwr_dword(gbase | mba_direct | 0x000ff400l,0x80000000l); memwr_dword(gbase | mba_direct | 0x000ff404l,0x00000000l);//border color index memwr_dword(gbase | mba_direct | 0x000ff408l,0x000000000);//pixel clock pll memwr_dword(gbase | mba_direct | 0x000ff40cl,0x00000afbl);//serial pll 32.9542 memwr_dword(gbase | mba_direct | 0x000ff410l,0x00000000l);//cfg reg memwr_dword(gbase | mba_direct | 0x000ff414l,0x00000000l);//graphics format(bits/pix) memwr_dword(gbase | mba_direct | 0x000ff418l,0x00000206l);//cursor x position memwr_dword(gbase | mba_direct | 0x000ff41cl,0x00000000l);//reserved pacdac c ontroller sample master structure setup btv2115 brook t ree 210 bt memwr_dword(gbase | mba_direct | 0x000ff420l,0x00000000l);//graphics diag reg memwr_dword(gbase | mba_direct | 0x000ff424l,0x00000000l);//softvideo diag reg memwr_dword(gbase | mba_direct | 0x000ff428l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff42cl,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff430l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff434l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff438l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff43cl,0x00000000l);//fifo error status memwr_dword(gbase | mba_direct | 0x000ff440l,0x80000010l);//change address to 0x10 memwr_dword(gbase | mba_direct | 0x000ff444l,0x00000000l);//video format reg memwr_dword(gbase | mba_direct | 0x000ff448l,0x00000000l);//vid 1 color key reg memwr_dword(gbase | mba_direct | 0x000ff44cl,0x00000000l);//vid 1 color key mask memwr_dword(gbase | mba_direct | 0x000ff450l,0x00000000l);//vid 1 x scale memwr_dword(gbase | mba_direct | 0x000ff454l,0x00000000l);//vid 2 color key memwr_dword(gbase | mba_direct | 0x000ff458l,0x00000000l);//vid 2 color key mask memwr_dword(gbase | mba_direct | 0x000ff45cl,0x00000000l);//vid 2 x scale memwr_dword(gbase | mba_direct | 0x000ff460l,0x00000000l);//vid y scale increment memwr_dword(gbase | mba_direct | 0x000ff464l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff468l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff46cl,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff470l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff474l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff478l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff47cl,0x80000200l);//change address 0x200 memwr_dword(gbase | mba_direct | 0x000ff480l,0x00000000l);//border color reg memwr_dword(gbase | mba_direct | 0x000ff484l,0x00000000l);//cursor color 1 memwr_dword(gbase | mba_direct | 0x000ff488l,0x00000000l);//cursor color 2 memwr_dword(gbase | mba_direct | 0x000ff48cl,0x00000000l);//cursor color 3 memwr_dword(gbase | mba_direct | 0x000ff490l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff494l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff498l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff49cl,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff4a0l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff4a4l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff4a8l,0x00000000l);//reserved memwr_dword(gbase | mba_direct | 0x000ff4acl,0x00000000l);//reserved brook t ree 211 bt cpu h ost b us i nterface vesa local bus interface the btv2115 interfaces to the cpu either via the video electronics standards as- sociation (vesa ? ) local bus (vl-bus ?) or the pci bus interface. for a descrip- tion of the pci interface, refer to ?ci bus interface?on page 216. the vesa local bus is an architectural, timing, electrical, and physical inter- face that allows the btv2115 to interface to the local bus of a host cpu. the vesa interface is de?ed in the following paragraphs. the overbar above a signal indi- cates that the signal is active-low. vl address bus vl_addr[31:2] ?these inputs provide the io port addresses or physical mem- ory addresses to the btv2115. vl byte enables vl_be[3:0 ] ?these inputs indicate which byte lanes of the 32-bit data bus are involved with the current vl-bus transfer. vl data bus vl_data[31:0] ?these inputs provide the bidirectional data path between the btv2115 and the cpu. during a read transfer operation, the btv2115 drives data onto vl_data[31:0]. byte enables vl_be[3:0] determine which byte lane(s) are valid. vl address strobe vl_ads ?this input indicates that a new cycle has begun. vl reset vl_reset ?this input is a master reset that is asserted after system power-up and before any valid cpu cycles begin. the vl_reset signal resets all functions on the btv2115 before execution. the relationship between the rising and falling edges of the vl_reset and the phase of vl_clock need not be guaranteed. vl clock vl_clock ?this clock signal is a 1x clock that follows the same phase as a 486-type cpu. the btv2115 supports the vesa local bus at up to 40 mhz. cpu h ost b us i nterface vesa local bus interface btv2115 brook t ree 212 bt vl memory or io status vl_m_io ?this cpu output signal indicates the type of access currently exe- cuting on the vl-bus. a high vl_m_io indicates a memory cycle; a low vl_m_io indicates an io cycle. vl data or code status vl_d_c ?this status signal indicates whether the current transfer contains data or code. vl read or write status vl_w_r ?this cpu output signal indicates the type of access currently execut- ing on the vl-bus. a high vl_w_r indicates a write; a low vl_w_r indicates a read. vl identi?r pin vl_id2 ?the vl-bus controller is capable of handling a high speed zero wait state write transfer. the btv2115 inserts a wait state when vl_id2 is low. vl ready return vl_rdyr tn ?this signal tells the btv2115 when the cycle has ended. vl local device select vl_ldev ?this output signal informs the vl-bus controller that the btv2115 recognizes the current cycle as an access to it. vl local ready vl_lrdy ?this input terminates the current active bus cycle and tells the vl- bus controller that the bus is done. if vl_id2 is set, the btv2115 starts driving vl_lrd y during the ?st t2 state for writes. most write cycles are completed in two clock cycles and vl_lrdy is driven low during the ?st t2 state. if vl_id2 is cleared, the btv2115 starts driving vl_lrdy in the second t2 state. interrupt request line 9 irq9 ?the irq9 line is a level-triggered interrupt that is electrically connected to irq9 on the isa bus. cpu h ost b us i nterface vl bus timing btv2115 brook t ree 213 bt vl bus timing this section presents timing diagrams for key vl waveforms. below, table 128 de?es the minimum and maximum values for the speci?d parameters. the following timing diagrams depict the associated vl time intervals. the variable z represents high-impedance. table 128. vl-bus timing symbol parameter max min units vl_clock (see figure 22) t 1 vl_clock rise time 3 ns t 2 vl_clock fall time 3 ns t 3 vl_clock high period 60% of t 5 40% of t 5 ns t 4 vl_clock low period 60% of t 5 40% of t 5 ns t 5 vl_clock period 25 ns vl_ads and vl_ldev (see figure 23) t 6 address, status, vl_ads setup to vl_clock 5 ns t 7 vl_ldev active delay from address, status (20pf loading) 20 ns t 8 vl_ldev inactive delay from address, status 20 ns vl_lrdy (see figure 24) t 9 vl_lrdy active delay from vl_clock 14 3 ns t 10 vl_lrdy inactive delay from vl_clock 14 3 ns t 11 vl_lrdy high before high-impedance (z) 60% of t 5 40% of t 5 ns data (see figure 25) t 12 read data setup to vl_clock 7 ns t 13 read data hold from vl_clock 2 ns cpu h ost b us i nterface vl bus timing btv2115 brook t ree 214 bt figure 22. vl_clock timing diagram figure 23. vl_ads and vl_ldev timing diagram vl_clock t 1 t 2 t 3 t 4 t 5 vl_clock t 6 t 7 vl_ads vl_ldev vl_lrdy z z t 8 vl_be[3:0] vl_addr[31:2] vl_w_r vl_m_io cpu h ost b us i nterface vl bus timing btv2115 brook t ree 215 bt figure 24. vl_lrdy delay timing diagram figure 25. data timing diagram vl_clock t 9 t 11 vl_lrdy z t 10 z vl_clock t 12 t 13 vl_data[31:0] cpu h ost b us i nterface pci bus interface btv2115 brook t ree 216 bt pci bus interface the pci local bus is an architectural, timing, electrical, and physical interface that allows the btv2115 to interface to the local bus of a host cpu. the supported pci bus cycles are as follows: i/o read i/o write memory read memory write con?uration read con?uration write memory read multiple memory read line memory write and invalidate memory write and memory write and invalidate are treated in the same man- ner. memory read and memory read multiple are treated in the same manner. the unsupported pci bus cycles are as follows: interrupt acknowledge special cycle dual address cycle all i/o, memory, and con?uration writes are three clock cycles unless held off by a full host fifo. the only two cycle writes are de?ed by grp_cfg6[7], see table 20 on page 48. subsequent writes in the same transaction are zero wait states as long as the internal fifo is not full. the pci bus interface pins are de?ed in the following paragraphs. the overbar above a signal indicates active-low. the term ?ustained tri-state ? ?is used in this section. it is de?ed as an active- low, tri-state signal owned and driven by a single agent at a time. the agent that drives this pin low must drive it high for at least one clock before allowing it to ?at. a new agent cannot start driving a sustained tri-state signal sooner than one clock after the previous owner tri-states it. to sustain the inactive status until a new agent drives it, a pullup must be provided by the central resource. pci address and data bus pci_ad[31:0] ?this tri-state, bi-directional, io pin handles both address and data information. a bus transaction consists of an address phase followed by one or more data phases for either read or write operations. the address phase is the clock cycle in which pci_frame is ?st asserted. during the address phase, pci_ad[31:0] contains a byte address for io operations and a dword address for con?uration and memory operations. during data phas- cpu h ost b us i nterface pci bus interface btv2115 brook t ree 217 bt es, pci_ad[7:0] contains the least signi?ant byte and pci_ad[31:24] contains the most signi?ant byte. read data is stable and valid when pci_trdy is asserted and write data is sta- ble and valid when pci_irdy is asserted. data is transferred during the clocks when both pci_trdy and pci_irdy are asserted. pci bus command and byte enables c_be [3:0] ?these tri-state, bi-directional, io pins handle both bus command and byte enable information. during the address phase of a transaction, c_be [3:0] contain the bus command. during the data phase, c_be [3:0] are used as byte en- ables. the byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. c_be [3] refers to the most signi?ant byte and c_be [0] refers to the least signi?ant byte. pci parity pci_p ar ?this tri-state, bi-directional, io pin provides even parity across pci_ad[31:0] and c_be [3:0]. this means that the number of 1 s on pci_p ar , pci_ad[31:0], and c_be [3:0] equals an even number. pci_p ar is stable and valid one clock after the address phase. for data phases, pci_p ar is stable and valid one clock after either pci_trdy is asserted on a read or pci_irdy is asserted on a write. once valid, pci_p ar remains valid until one clock after the completion of the current data phase. p ci_p ar and pci_ad[31:0] have the same timing, but pci_p ar is delayed by one clock. the btv2115 drives pci_p ar for read data phases; the master drives pci_p ar for address and write data phases. pci clock pci_clk ?this input provides timing for all pci transactions. all pci signals except pci_reset and the optional interrupt are sampled on the rising edge of pci_clk, and all other timing parameters are de?ed with respect to this edge. the btv2115 supports a pci clock of up to 33 mhz. pci reset pci_reset ?this input resets all functions on the btv2115 before execution. pci_reset may be asynchronous to pci_clk when asserted or deasserted. pci cycle frame pci_frame ?this sustained tri-state signal is driven by the current master to indicate the beginning and duration of an access. p ci_frame is asserted to signal the beginning of a bus transaction. data transfer continues throughout assertion. at deassertion, the transaction is in the ?al data phase. pci initiator ready pci_irdy ?this sustained tri-state signal indicates the bus master s readiness to complete the current data phase. pci_irdy is used in conjunction with pci_trdy . when both pci_irdy and pci_trdy are asserted, a data phase is completed on that clock. during a read, pci_irdy indicates when the initiator is ready to accept data. during a write, pci_irdy indicates when the initiator has placed valid data on pci_ad[31:0]. wait cycles are inserted until both pci_irdy and pci_trdy are asserted togeth- er. cpu h ost b us i nterface pci bus interface btv2115 brook t ree 218 bt pci target ready pci_trdy ?this sustained tri-state signal indicates the btv2115 s readiness to complete the current data phase. pci_ ir dy is used in conjunction with pci_trdy . when both pci_irdy and pci_trdy are asserted, a data phase is completed on that clock. during a read, pci_ t rdy indicates when the target is presenting data. during a write, pci_ tr dy indicates when the target is ready to accept the data. wait cycles are inserted until both pci_irdy and pci_trdy are asserted together. pci stop pci_st op ?this sustained tri-state signal indicates the btv2115 is requesting the master to stop the current transaction. pci initialization device select pci_idsel ?this input is used to select the btv2115during con?uration read and write transactions. pci device select pci_devsel ?this sustained tri-state signal indicates device selection. the btv2115 always asserts pci_devsel in the third clock cycle, except in cases of two-clock writes. when actively driven, p ci_devsel indicates the driving device has decoded its address as the target of the current access. pci interrupt a pci_int a ?this signal is an open drain interrupt output. pci high speed read hsread ?when the host is the destination, an input of 1 allows high speed read of gui blit data. a 0 input disables the high speed read. this signal should be set to 1 only if the pci bus clock is at or above 16 mhz, and should be stable during btv2115 operation. cpu h ost b us i nterface pci con?uration space btv2115 brook t ree 219 bt pci con?uration space the pci con?uration space de?es the registers used to interface between the host and the pci local bus. this section de?es the organization of the registers within the 64 byte prede?ed header portion of the con?uration space. figure 26 shows the con?uration space header. for details on the pci bus, refer to the pci local bus speci?ation, revision 2 . the btv2115 is a multifunction device. function 0 responds as a vga graph- ics controller. function 1 responds as an audio device. in the paragraphs below, assume that the two functions have the same de?itions, unless speci?d. the con?uration space registers are stored in dwords and de?ed by byte ad- dresses. therefore a register one byte in length can have a bit de?ition other than 7:0 (for example 31:24), depending on its location in the con?uration space. for a discussion on con?uration cycle addressing, refer to section 3.6.4.1 of the pci local bus speci?ation, revision 2 . figure 26. pci con?uration space header device id vendor id status command class code revision id 00h 04h 08h 0ch 10h 14h 18h 1ch 20h 24h 28h 2ch 30h 34h 38h 3ch reserved reserved expansion rom base address reserved reserved interrupt pin interrupt line 31 16 15 0 base 0 register prefetch base register reserved reserved reserved cpu h ost b us i nterface pci con?uration space btv2115 brook t ree 220 bt all writable bits are reset to 0 by the system reset. after reset, the btv2115 is disabled and will only respond to cfgwr and cfgrd cycles. all reserved and unimplemented registers are read as zeroes. pci vendor id registers name: pci_vendor_id address: 01h:00h, read only size: 16 bit function: this register contains the unique vendor id assigned to brooktree cor- poration. this ?ld will always return the value of 109eh. pci device id registers name: pci_device_id address: 03h:02h, read only size: 16 bit function: this register contains the unique device id assigned by brooktree cor- poration. this ?ld will return the btv mediastream controller model number 2115 in hexadecimal. pci command registers name: pci_command0, pci_command1 address: 05h:04h, read/write as shown below size: 16 bit function: this register controls the ability to respond to pci cycles. the bit con- tents for function 0 (pci_command0) are shown in table 129. the bit contents for function 1 (pci_command1) are shown in table 130. table 129. pci command register - function 0 bit field detail 15:6 read only. contains all 0 s. 5 pci_snoop_dac 1 = enable snooping 4:2 read only. contains all 0 s 1 pci_mem_en 1 = enable memory cycles 0 = disable memory and rom cycles 0 pci_io0_en 1 = enable io cycles in the vga address space or alternate address space table 130. pci command register - function 1 bit field detail 15:1 read only. contains all 0 s. 0 pci_io1_en 1 = enable io cycles in the audio range cpu h ost b us i nterface pci con?uration space btv2115 brook t ree 221 bt pci status registers name: pci_status address: 07h:06h, read only size: 16 bit function: this register records status information for pci bus related events. the bit contents are shown in table 131. pci revision id register name: pci_revision_id address: 08h, read only size: 8 bit function: this register contains the revision id for the btv2115. the value is 03h. pci class code registers name: pci_class0_id, pci_class1_id address: 0b:09h, read only size: 32 bit function: this register identi?s the function of the btv2115. the bit contents for function 0 (pci_class0_id) are shown in table 132. the bit con- tents for function 1 (pci_class1_id) are shown in table 133. table 131. pci status register bit field detail 31:27 read only. contains all 0 s. 26:25 pci_devsel_ timing read only, set to 01. medium, devsel always in third clock or faster. 24 returns 0 23 pci_bk_to_bk read only, set to 1, supports back-to-back cycles. 22:16 read only. contains all 0 s. table 132. pci class code register - function 0 bit field detail 31:24 display controller = 03h alternate decode = ffh 23:16 vga - 00h 15:8 contains all 0 s. cpu h ost b us i nterface pci con?uration space btv2115 brook t ree 222 bt pci base address registers name: pci_base0_reg, pci_base1_reg address: 10h, read/write size: 8 bit function: the bit contents for pci_base0_reg, function 0, is shown in table 134. for function 1, pci_base1_reg is not implemented and is read as 32?00000000. when the following conditions are met during a memory cycle, the btv2115 is accessed: bits 31:25 are non-zero and match bits 31:25 of the gui base address, and memory cycles are enabled in the pci command register 0 (see table 129 on page 220). non-zero writes to this register will cause the assertion of the protected mode enable bit (grp_gui_base[24]). 32mb of cpu space is reserved for btv2115 operations. for more information on the address space, refer to ?pu address space ap- ertures?starting on page 97. pci prefetchable base address registers name: pci_pref_base0, pci_pref_base1 address: 14h, read/write size: 8 bit function: the bit contents for pci_pref_base0, function 0, is shown in table 135. for function 1, pci_ref_base1 is not implemented and reads back 32?00000000. table 133. pci class code register - function 1 bit field detail 31:24 multimedia device - 04h 23:16 audio - 01h 15:8 contains all 0 s. table 134. pci base register - function 0 bit detail 31:25 if all zeroes, btv2115 not accessible via memory cycles in a non- prefetchable range. if non-zero, speci?s the address of the 32mb gui base aperture space (pm_base). refer to ?ui base address register?on page 123. 24:4 read only, all 0 s 3 read only. 0 indicates not prefetchable. 2:1 read only. 00 indicates locatable anywhere in 32-bit address space. 0 read only. 0 speci?s memory space cpu h ost b us i nterface pci con?uration space btv2115 brook t ree 223 bt when the following conditions are met during a memory cycle, the btv2115 is accessed: bits 31:25 are non-zero and match bits 31:25 of the gui base address, and memory cycles are enabled in the pci command register 0 (see table 129 on page 220). non-zero writes to this register will cause the assertion of the protected mode enable bit (grp_gui_base[24]). 32mb of cpu space is reserved for btv2115 operations. for more information on this address space, refer to ?pu address space ap- ertures?starting on page 97. grp_pbase is the vga register that reads the ad- dress speci?d by bits [31:25]; refer to ?ead pci prefetchable base address register?on page 59. pci rom base address register name: pci_rom_base0, pci_rom_base1 address: 33h:30h, read/write size: 32 bit function: these registers specify a 16mb space for the btv2115 to respond to rom cycle requests. these registers are valid for function 0 only. for function 1, these registers are not implemented and read back as 32?00000000. the bit contents for pci_rom_base0, function 0, is shown in table 136. grp_rombase is the vga register that reads the address speci?d by bits [31:24]; refer to ?ead pci rom base address register?on page 59. table 135. pci prefetch base register - function 0 bit detail 31:25 if all zeroes, btv2115 not accessible via memory cycles in a non- prefetchable range. if non-zero, speci?s the address of the 32mb gui base aperture space (pm_base). refer to ?ui base address register?on page 123. 24:4 read only, all 0 s 3 read only. 1 indicates prefetchable. 2:1 read only. 00 indicates locatable anywhere in 32-bit address space. 0 read only. 0 speci?s a memory space indicator table 136. pci rom base register - function 0 bit detail 31:24 speci?s a 16mb space for rom cycles. 23:1 reserved 0 pci_rom_en, read/write 1 = rom cycles enabled 0 = rom cycles disabled cpu h ost b us i nterface pci con?uration space btv2115 brook t ree 224 bt pci interrupt line register name: pci_int_line[7:0] address: 3ch, read/write size: 8 bit function: this register speci?s which system interrupt controller input is con- nected to the btv2115 s interrupt pin. this register is valid for function 0 only. for function 1, this register is not implemented and is read as 8?00. pci interrupt pin register name: pci_int0_pin, pci_int1_pin address: 3dh, read only size: 8 bit function: for function 0, this register returns the value 8?01, which indicates a response on pci_int a only. for function 1, this register is not imple- mented and returns 8?00. brook t ree 225 bt v ideo ram i nterface introduction the btv2115 provides data steering, addressing, timing, and control for an exter- nal memory bus to which 1 - 4 mb of dual ported video ram, rom, and an op- tional yamaha ? fm synthesizer are attached. the memory bus provides access to the multimedia data and control information stored in vram, as well as rom and yamaha data. the btv2115 attaches to the parallel port of the vram array via the memory bus. the btv2115 does not attach to the vram serial data port, even though it controls all the accesses to vram, both parallel and serial (between the vram serial port and the btv2 487 pacdac). in addition, the btv2115 provides the ability to write flash rom to simplify bios upgrades. an internal btv2115 bus is used to steer data between the external memory bus, the multi-media bus (btv2811a and btv2300), and internal btv2115 sub-mod- ules. these internal sub-modules provide the functionality of btv2115, including buffering and steering of data between the cpu bus and the other components. several types of vram are supported. the type of vram used in the sub- system design is con?urable at the btv2115 pins via strapable bits. the vram type determines the vram parameter bits (such as speed, size, and write/cas con?uration) in the con?uration registers. these initial values can be overrid- den, if necessary, by software. v ideo ram i nterface vram signal description btv2115 brook t ree 226 bt vram signal description the external memory bus includes 32 bidirectional (tristate) data lines, 9 address lines, 4 ras (row address strobe) lines, 6 control lines to generate cas (column address strobe) and we (write enable), 1 vram output enable, and 1 vram special function select signal. the vram data lines double as con?uration strap- ping bits, with mdata optionally tied through 20k ohm external resistors to v dd or gnd and sampled at reset to provide board-dependent initial values for many of the con?uration register bits. (note: pci-bus attachment uses a different method of setting initial values.) the cas[3:0] and we[1:0] pins on the btv2115 are bimodal. based on the vram type con?ured, the btv2115 maps the column address strobe and write enable functions to the appropriate btv2115 pins to allow the same board wiring for either dual cas or dual we memories in the same board design without jump- ers or straps in the memory subsystem. the naming convention for the btv2115 assumes the ?ual cas?mode, how- ever the cas[3:0] and we[1:0] pins have different functions in dual cas or dual we mode. below, table 137 summarizes the vram dual we/dual cas modes. table 138 provides the vram bus signals. table 137. vram dual we/dual cas modes btv2115 pin name function: dual cas mode function: dual we mode cas0 column address strobe byte 0 write enable byte 0 cas1 column address strobe byte 1 column address strobe byte 0 & 1 cas2 column address strobe byte 2 write enable byte 2 cas3 column address strobe byte 3 column address strobe byte 2 & 3 we0 write enable byte 0 & 1 write enable byte 1 we1 write enable byte 2 & 3 write enable byte 3 v ideo ram i nterface vram signal description btv2115 brook t ree 227 bt table 138. vram bus signals name # description i/o mdata[31:8] 24 bidirectional tri-state vram memory data, address lines for flash rom and register selects for yamaha fm synthesizer are multiplexed on mdata[27:8]. i/o mdata[7:0] 8 bidirectional tri-state vram , rom, and yamaha data. i/o maddr[8:0] 9 multiplexed row and column address. o ras [3:0] 4 vram row address strobe (ras). o cas0 1 dual cas: vram column address strobe (cas) for the least signi?ant byte of the 32 bit data bus. o dual we: write enable (we) for byte0. cas1 1 dual cas: vram column address strobe (cas) for byte1. o dual we: cas for least signi?ant 16 data bits (byte1 and byte0). cas2 1 dual cas: vram column address strobe (cas) for byte2. o dual we: write enable (we) for byte2. cas3 1 dual cas: vram column address strobe (cas) for byte3. o dual we: cas for most signi?ant 16 data bits (byte3 and byte2). w e0 1 dual cas: we for least signi?ant 16 data bits (byte1 and byte0). also used as write control for flash rom and oplx. o dual we: write enable (we) for byte1. also used as write control for flash rom and oplx. w e1 1 dual cas: we for most signi?ant 16 data bits (byte3 and byte2). o dual we: write enable (we) for byte3. tr g 1 vram transfer enable. trg is also used as read control for flash rom and oplx. o dsf 1 vram special function select. o v ideo ram i nterface vram con?urability btv2115 brook t ree 228 bt vram con?urability in order to simplify board design with various vram con?urations, the btv2115 is implemented with internal con?uration registers containing memory parameters, including different memory speeds (80, 70 or 60 nanosecond parts), 8 or 16 millisecond refresh period, etc. these con?uration bits are initialized based on the vram type which is set at reset by strapping mdata[15:10] using 20k ohm resistors. the con?uration registers which are initialized using this strapping mechanism are also accessible by the host cpu. it is possible to alter the powerup con?uration after reset via the bios initialization. vram types supported table 139 describes the types of vram supported. the dual cas and 2mbit cbr values are set by strap resistors. the other values are set by bios. refer to ?on?uration registers?on page 133. v ideo ram i nterface vram con?urability btv2115 brook t ree 229 bt table 139. supported vram types (1 of 2) part# vendor dual cas ram speed 2 mbit cbr sam length block mode tms55160-80 texas instruments 1 00 0 0 1 tms55160-70 texas instruments 1 01 0 0 1 tms55160-60 texas instruments 1 10 0 0 1 tms55165-80 texas instruments 0 00 0 0 1 tms55165-70 texas instruments 0 01 0 0 1 tms55165-60 texas instruments 0 10 0 0 1 ibm025160l-70 ibm 1 01 0 0 0 ibm025160l-80 ibm 1 00 0 0 0 ibm025161l-70 ibm 1 01 0 0 0 ibm025161l-60 ibm 1 10 0 0 0 upd482445-80 upd482444-80 nec 000010 upd482445-70 upd482444-70 nec 001010 upd482445-60 upd482444-60 nec 010010 hm538253-80 hitachi 0 00 0 1 1 hm538253-70 hitachi 0 01 0 1 1 km428c256-80 samsung 0 00 0 1 1 km428c256-70 samsung 0 01 0 1 1 km428c256-60 samsung 0 10 0 1 1 km428c257-80 samsung 0 00 0 1 1 km428c257-70 samsung 0 01 0 1 1 km428c257-60 samsung 0 10 0 1 1 tc528257-80 toshiba 0 00 0 1 1 tc528257-70 toshiba 0 01 0 1 1 v ideo ram i nterface vram con?urability btv2115 brook t ree 230 bt upd482234-80 nec 0 00 0 1 1 upd482234-70 nec 0 01 0 1 1 upd482235-80 nec 0 00 0 1 1 upd482235-70 nec 0 01 0 1 1 table 139. supported vram types (2 of 2) part# vendor dual cas ram speed 2 mbit cbr sam length block mode v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 231 bt vram parallel data cycle types supported the btv2115 is designed to control a btv mediastream family of chips. in the design, the timing speci?ations of the supported vram types are satis?d, with- in the load limitations for the subsystem implementation (see ?perating speci? cations?on page 317 for the design speci?ations). the types of vram cycles which are generated by the btv2115 are shown in the following diagrams. the di- agrams show relative timings; the internal 50 mhz clock is shown for reference. the diagrams which follow use a signal naming convention that assumes the btv2115 is con?ured for ?ual cas?mode. the relative timings for the column address strobe and write enable functions are accurate for both the dual cas and dual write enable modes. in the following timing diagrams, the term ?ram?refers to the dram por- tion of the vram. refresh cycle the btv2115 issues cas-before-ras refresh (cbrr) cycles with option re- set. figure 27. vram refresh cycle 50mhz ras[3:0] cas [3:0] dsf 20ns v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 232 bt dram read 1 to 4 bytes transferred from memory to the mdata bus. figure 28. vram read cycle (80ns cycle timing) maddr 50mhz ras x cas x trg mdata we x dsf row column valid 20ns v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 233 bt figure 29. vram read cycle (70ns cycle timing) maddr 50mhz ras x cas x trg mdata we x dsf 20ns column row valid v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 234 bt dram write 1 to 4 bytes transferred from the mdata bus to memory. non-block btv2115 writes use masked (write-per-bit) mode exclusively (selected by we =0 at ras fall). in write-per-bit mode, the vram ands a mask with the data bits, allowing selective writing of bits. this mask can be provided through an internal mask reg- ister in vram, or by sampling the data lines at ras fall. the btv2115 does not support use of the internal vram mask register. the btv2115 has its own mask register addressable in i/o space. this mask is used whenever bit level writes are needed, and is set to all ones for other writes. figure 30. vram read cycle (60ns cycle timing) maddr 50mhz ras x cas x trg mdata we x dsf column row valid 20ns v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 235 bt the btv2115 uses only non-persistent write-per-bit mode (we =0 at ras fall) for writes. the vram persistent mask register is not written; a mask value is d riv- en by the btv2115 (and forced to all ones during ?ormal?cycles when write-per- bit is not needed). figure 31. dram masked write cycle (80ns cycle timing) maddr 50mhz ras x cas x mdata we x dsf column row valid 20ns mask v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 236 bt the btv2115 uses only non-persistent write-per-bit mode (we =0 at ras fall) for writes. the vram persistent mask register is not written; a mask value is driv- en by the btv2115 (and forced to all ones during ?ormal?cycles when write-per- bit is not needed). figure 32. dram masked write cycle (70ns cycle timing) maddr 50mhz ras x cas x mdata we x dsf column row valid 20ns mask v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 237 bt the btv2115 uses only non-persistent write-per-bit mode (we =0 at ras fall) for writes. the vram persistent mask register is not written; a mask value is driv- en by the btv2115 (and forced to all ones during ?ormal?cycles when write-per- bit is not needed). figure 33. dram write cycle (60ns cycle timing) maddr 50mhz ras x cas x mdata we x dsf column row valid 20ns mask v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 238 bt load color register the color register contents are used during block writes. w e =1 and dsf =1 at ras fall causes a vram register load, and dsf=1 at cas fall selects the color register. the mdata value present at cas fall is then loaded into the vram color register for later use in block write cycles. the btv2115 does not use the internal vram mask register selectable when dsf=0 at cas fall. dram non-masked block write used to write the previously loaded color register value into dram. micron block mode increases eightfold the number of locations concurrently written to vram by af fecting a block of 8 columns (instead of a single column). this is made possible by using each enabled byte transferred from the mdata bus (at normal write data sample time) as a column mask, controlling 8 consecutive columns (ignoring the low 3 column address bits sampled at cas fall, instead of selecting 1 of 8 columns). each byte of column mask affects the block of 8 col- umns for a group of 8 data bits. ti block mode quadruples the number of locations concurrently written to vram by affecting a block of 4 columns (instead of a single column). this is made possible by using the halves of each enabled byte transferred from the mda- ta bus (at normal write data sample time) as a column mask, controlling 4 con- secutive columns (ignoring the low 2 column address bits sampled at cas fall, instead of selecting 1 of 4 column). each half byte of column mask affects the block of 4 columns for a group of 4 data bits (1 quadrant). figure 34. load color register cycle (all speeds) maddr 50mhz ras x cas x mdata we x dsf column row valid 20ns v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 239 bt non-masked mode is selected by trg =1, we =1, and dsf=0 at ras fall. block mode is then selected by dsf=0 at cas fall. masked write (write-per-bit) mode is selected when we =1 and dsf=0 at ras fall of a non-refresh dram cycle. block mode is selected when dsf=1 at cas fall during a non-refresh dram cycle. figure 35. dram non-masked block write cycle (80ns cycle timing) maddr 50mhz ras x cas x mdata we x dsf column row valid 20ns v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 240 bt masked write (write-per-bit) mode is selected when we =1 and dsf=0 at ras fall of a non-refresh dram cycle. block mode is selected when dsf=1 at cas fall during a non-refresh dram cycle. figure 36. dram non-masked block write cycle (70ns cycle timing) maddr 50mhz ras x cas x mdata we x dsf column row valid 20ns v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 241 bt masked write (write-per-bit) mode is selected when we =1 and dsf=0 at ras fall of a non-refresh dram cycle. block mode is selected when dsf=1 at cas fall during a non-refresh dram cycle. figure 37. dram non-masked block write cycle (60ns cycle timing) column row valid 20ns maddr 50mhz ras x cas x mdata we x dsf v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 242 bt register transfer (dram to sam) data transferred (internal to the vram) from dram to the sam serial data register. selected by trg =0 (and cas =1) and dsf=0 at ras fall. the sam data can then be output through the vram serial data bus to btv2 487. trg =0 and we =1 at ras fall during a non-refresh cycle selects the operation which transfers a data row from dram into the vram internal serial data regis- ter. figure 38. dram memory-to-register transfer cycle (80ns cycle timing) maddr 50mhz ras x cas x trg mdata we x dsf column row 20ns v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 243 bt figure 39. vram memory-to-register transfer cycle (70ns cycle timing) maddr 50mhz ras x cas x trg mdata we x dsf column row 20ns v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 244 bt figure 40. vram memory-to-register transfer cycle (60ns cycle timing) maddr 50mhz ras x cas x trg mdata we x dsf column row 20ns v ideo ram i nterface vram parallel data cycle types supported btv2115 brook t ree 245 bt page mode cycles the btv2115 supports page mode cycles for read, write, and block write modes, as shown in figure 41. vram timing considerations the btv2115 is designed to work properly on a board meeting the minimum and maximum load limits for the btv subsystem design (see ?ram timing param- eters?on page 317). the btv2115 uses an on-chip phase-locked loop to quadruple the input 25mhz clock, producing internal 100mhz and 50mhz clocks. the vram control signals (as well as input address and data lines) are then generated off the rising edge of the internal 100mhz clock, producing a high degree of ac- curacy. the timing diagrams for the btv2115 memory cycle types supported show the nominal placement of signals referenced to the internal 50 mhz clock. the btv2115 meets the timing speci?ations for the vram types supported. timing values for signals generated by the btv2115 are contained in. for compar- ison and detailed explanation of the corresponding vram parameters, see the speci?ations for the supported vram part number. figure 41. page mode cycles maddr 50mhz ras x cas x trg mdata we x dsf 20ns { { { write read block write v ideo ram i nterface non-vram attachment btv2115 brook t ree 246 bt non-vram attachment the vram bus also supports single byte interface connection of rom and the yamaha fm synthesizer. the vram bus does not provide a general purpose at- tachment. it is for special purpose attachment, designed with careful loading con- siderations. because of the load on the vram address lines at the full 8 module limit, addressing for rom and yamaha is provided by connecting to the higher or- der data lines. the rom (a19 to a0) address lines are connected to the mdata bus (bits 27:8). the yamaha (a2 to a0) address lines are connected to the mdata bus (bits 10:8). the address values are multiplexed by the btv2115 during read and write cycles. both rom and yamaha occupy a 1mb address space with a single chip select generated for any address within that space. the btv2115 supports several types of rom, but only a single rom module can be driven directly (due to a single 1m chip select). external logic would be required to generate additional distinct chip selects. rom con?urability the btv2115 supports attachment of several different rom t ypes, generating control signals at two different speeds. con?uration register grp_cfg1[5] (see table 25 on page 53) sets the rom speed, which is strapable at reset time on mdata[16]. the btv2115 will set the rom speed bit at fast or slow, based on the rom type. parts with speeds above the fast threshold will use the 45ns cycle, while parts below the threshold will be con?ured as slow and will run with the 70ns timing. the btv2115 supports the 2700 family of non-flash roms (proms) and the flash roms listed in table 140. note opl2 has only 2 registers and opl3 has 4 registers; neither has an a2 pin, thus, no connection to mda- ta[10]. table 140. flash rom types supported part # description am29f010-70 amd flash rom 128kx8 70ns am29f010-120 amd flash rom 128kx8 120ns i28f010-70 intel flash rom 128kx8 70ns i28f020-120 intel flash rom 256kx8 120ns v ideo ram i nterface non-vram attachment btv2115 brook t ree 247 bt rom connection in addition to normal rom, the btv2115 can utilize flash memory for bios code, allowing software upgrade. the rom is addressable at an offset of +7mb above the gui base address 32m address boundary, that is, a rom cycle is se- lected with fba map = 00 and submap = 111. it is also addressable at the vga rom address. figure 42 shows the signal connections for a typical flash rom. we 0 is used only for flash rom w rites. figure 42. rom connection ce oe we a16 a15:8 mdata[7:0] d7:0 a7:0 mdata[23:16] mdata[15:8] mdata24 bios_ c s trg we 0 0 1 2 19 20 24 31 23 22 . . . . . . 25 gui base fba 21 . . . 0 31 cpu address vram address/control 1m 8m 32m 0 0 1 1 1 map submap v ideo ram i nterface non-vram attachment btv2115 brook t ree 248 bt rom read cycle the btv2115 reads rom data at two different speeds corresponding to 70ns and 120ns access times. rom address bits a19-a0 are connected to mdata[27:8] due to load limita- tions on vram bus addresses. depending on rom size, some of the bits are not be connected. figure 43. rom read cycle (70ns part) 50mhz bios_ cs we 0 20ns trg rom address mdata[27:8] valid mdata[7:0] v ideo ram i nterface non-vram attachment btv2115 brook t ree 249 bt rom address bits a19-a0 are connected to mdata[27:8] due to load limita- tions on vram bus addresses. depending on rom size, some of the bits are not be connected. figure 44. rom read cycle (120ns part) 50mhz bios_ cs we 0 20ns trg rom address mdata[27:8] valid mdata[7:0] v ideo ram i nterface non-vram attachment btv2115 brook t ree 250 bt flash rom write cycle the btv2115 supports writing of flash rom data at two different speeds. the special sequence necessary to write flash rom is supported by the btv2115 bios. rom address bits a19-a0 are connected to mdata[27:8] due to load limita- tions on vram bus addresses. depending on rom size, some of the bits are not be connected. figure 45. flash rom write cycle (70ns part) 50mhz bios_ cs we 0 20ns trg rom address mdata[27-8] write data mdata[7:0] v ideo ram i nterface non-vram attachment btv2115 brook t ree 251 bt rom address bits a19-a0 are connected to mdata[27:8] due to load limita- tions on vram bus addresses. depending on rom size, some of the bits may not be connected. figure 46. flash rom write cycle (120ns part) 50mhz bios_ cs we 0 20ns trg rom address mdata[27:8] write data mdata[7:0] v ideo ram i nterface non-vram attachment btv2115 brook t ree 252 bt yamaha con?urability the yamaha ymf278 (opl4), ymf262 (opl3), and ym3812 (opl2) fm syn- thesizers can easily be connected in a btv subsystem (as shown in figure 47). the opl4 has an additional register select (address) bit to support new registers. yamaha fm synthesizer connection the yamaha data lines are connected to the low byte of the vram data (mdata[7:0]). data is steered by the internal btv2115 memory controller to/ from the proper system byte during yamaha register accesses. the register selects do not connect to vram address bits (due to address loading), but connect to vram data bits (mdata[10:8]), which are multiplexed to contain the proper addressing information for the register selects. figure 47. btv2115 connections to yamaha fm synthesizer note yamaha must also be connected to other chips in the btv subsystem. those connections are not shown here. legacy audio supports the yamaha 2 and 4 operator mode fm synthesizer chip family, with direct support for opl3. mdata[7:0] mdata[9:8] we 0 trg 7:0 a1:a0 mdata[10] a2 wr 0 1 2 19 20 24 31 23 22 . . . . . . 25 gui base fba 21 . . . 0 31 cpu address vram address/control 1m 8m 32m 0 0 0 1 1 map submap opl_irq rd opl_cs cs brook t ree 253 bt v ideo i nput s ubsystem introduction the btv2115 s video input subsystem interfaces between the btv2811a video decoder and the memory controller and vram via the memory bus. within the video input subsystem, the video input logic takes a continuous byte stream of video (mm_data) from the btv2811a, extracts the encoded control informa- tion, formats the pixel streams, and packs it into the speci?d vram buffer. fig- ure 48 shows an overview of the video input subsystem. within the vram, a control structure list controls the video input logic. this dma channel command-like architecture provides a great deal of ?xibility to capture and display programs. the video input subsystem accesses the control structure list via the video ad- dress register ( var), which points to the top of the list. the dword at the top of the list (the init structure) contains initial control values. each control structure in the list consists of three sequentially located dwords of vram. thus, figure 49 represents a typical control structure list. figure 48. video input subsystem m emory b us 8 mm_data mm_clk v ideo i nput s ubsystem t o : m emory c ontroller and vram v ideo i nput s ubsystem introduction btv2115 brook t ree 254 bt the end_of_list bit of the video input control structure indicates the end of the video control structure list. when a control structure is completed with this bit set, the var starts the process over again. any control structure can be marked to ex- ecute an interrupt upon completion. in addition, control structures can specify cov- erage of either vertical active lines or vertical blank lines, such as the vertical interval-time code marker or closed captioning information. each control structure can have unique a capture format. for example, closed captioning data can be captured in mono format (y only) while the active vertical lines are captured in 4:2:2 ycrcb format. in addition, a structure can be marked to drop speci?d lines of a speci?d ?ld by marking off the required time without actually storing data into the vram, thus, easily skipping over either odd or even ?lds. the btv2811a provides the byte stream protocol that describes the video im- age delivered to the btv2115 controller. the btv2811a encoded information in- cludes factors such as vertical reset, horizontal scaling, and vertical decimation. a byte stream decoder within the btv2115 s video input logic reconstructs the two dimensional video image and any associated data, e.g. closed captioning, from this incoming byte stream. the desired portions of the data can be converted from 4:2:2 ycrcb into 4:1:1 or mono only and then packed into vram to minimize size/bandwidth. in addition, the pixels can remain in 4:2:2 format or can be deci- mated vertically and horizontally by a factor of 4. this further decimation is useful for obtaining icon-sized live video. figure 49. video input control structures video address init structure control structure control structure last control structure register (var) v ideo i nput s ubsystem introduction btv2115 brook t ree 255 bt the video input control structure list can be used to control double buffering for both the video capture and video display processes of the pacdac controller. for video display, control of the a/b buf fer selection of the pacdac controller video 1 fifo or video 2 fifo can be controlled by completion of a capture structure. as shown in figure 50, the btv2811a data is presented to the byte stream de- coder block which interprets the packed format into a valid pixel stream with sur- rounding video frame control signals extracted. the pixel stream is formatted and decimated into dwords destined for the vram media buffer. as each dword is formed, it is inserted into the 16x32 fifo and passed from the video clock domain to the btv2115 internal mclk domain. on the mclk side, a ?ite state machine is in overall control of all aspects of the video input subsystem. it traverses the structure list, fetches each control or init structure in turn and presents the various ?lds, and handles the writing of the vid- eo data from the 16x32 fifo to vram. figure 50. video input subsystem block diagram mm_data[7:0] mm_clk p acker c lock m ux 4:2:2 16x32 m emory b us f inite i nterface s tate m achine m emory b us 4:2:2 4:1:1 mono mclk 50mh z c lock d omain v ideo c lock d omain b yte s tream d ecoder 16 16 16 p arallel i nterface d ecoder 16 8 8 mm_data[23:8] v ideo i nput s ubsystem buffer management hardware btv2115 brook t ree 256 bt buffer management hardware the video input registers share the audio subsystem s submap 5 (see figure 12 on page 116). video control register name: aud_vcr address: gbase | 005003c0h, read/write size: 8 bit function: this register contains various control bits for the video input function as shown in table 141. video one register name: aud_v1r address: gbase | 005003c1h, read/write size: 8 bit function: this single bit in this register drives the pacdac controller s video1 buffer address logic to select either video fifo 1 a pointer or b point- er. this allows direct software control of double buffering for the video table 141. video control register bit field name description 7 enable video 0= reset video subsystem 1= enable video input processing. this bit should be held at zero until after clock selection is made by aud_vcr[6] this bit is reset by the pause function in the control structures. 6 clock select 0= use 50mhz mclk 1= use video input clock, i.e. the mm_clk. set this bit to one if a btv2811a is known to be present from i 2 c inquiries. once the clock bit is set then the enable bit, aud_vcr[7] can be set on a subsequent i/o operation. 5:3 reserved 2 enable parallel decoder pci-bus only 0 = btv2811a interface 1= parallel decoder interface (see ?aral- lel decoder interface?on page 266) 1:0 reserved v ideo i nput s ubsystem buffer management hardware btv2115 brook t ree 257 bt window associated with video fifo one in the btv2487. notice that the state of this bit can also be automatically controlled by bits in the video input control structure, below. video two register name: aud_v2r address: gbase | 005003c2h, read/write size: 8 bit function: this single bit in this register drives the pacdac controller s video2 buffer address logic to select either video fifo 2 a pointer or b point- er. this allows direct software control of double buffering for the video window associated with video fifo two in the btv2487. notice that the state of this bit can also be automatically controlled by bits in the video input control structure, below. video address register name: va r address: gbase | 005003c4h, read/write size: 32 bit function: the structure address ?ld in this register is used at the end of every video capture list to know where to begin the next capture list. the bit contents of this registers are shown in table 144. table 142. video one register bit description 7:1 reserved 0 select pacdac controller video fifo 1 b. this bit can be set or reset by the video structures. 0 = use video buffer a on video fifo 1 at the top of next frame 1 = use video buffer b on video fifo 1 at the top of next frame table 143. video two register bit description 7:1 reserved 0 select pacdac controller video fifo 2 b. this bit can be set or reset by the video structures. 0 = use video buffer a on video fifo 2 at the top of next frame 1 = use video buffer b on video fifo 2 at the top of next frame v ideo i nput s ubsystem buffer management hardware btv2115 brook t ree 258 bt init structure de?ition the btv2811a s vertical timing loop allows the number of lines in the vertical ac- tive region to vary if the btv2811a is decoding a video tape recorder in any mode other than normal play. as a result, the btv2811a provides an accurate leading edge detection of vertical active. however the number of lines expected may dif- fer, and the actual leading edge of vertical active could be on an unexpected line. to make the control structure selection of starting line values work correctly, the vertical line counter in the byte stream decoder is reloaded from the value in the init structure whenever the ?st vertical active horizontal reset is detected. normally, active video for an ntsc signal starts on line 22. when a video tape re- corder is in a mode other than normal play, the active video may not start until much later (for example, line 28). if a capture control structure is coded to start capture on line 22 but active video does not actually start until line 28, six lines of inactive video would be captured. to circumvent this, the vert_reload value should be programmed to a larger value (for example, line 32) and the capture control structure set to start at that same value. when the btv2115 detects the start of vertical active data, it will set its internal line counter to 32 (in this example) and start capturing data for the capture control structure. table 144. video address register bit(s) field name description 31:22 current tag read only view of tag ?ld of control structure in process. reset to zero by chip reset. not de?ed when enable video (bit 7, video control) is not set. 21:2 structure address vram dword address of ?st structure in the control structure list. note: this always points to an init structure followed by a variable number of control structures. 1:0 reserved table 145. init structure bit(s) field name description 31:30 reserved 29:20 blank_src_pixels max number of video source pixels that can be captured on a vertical blanked line. 19:10 active_src_pixels max number of video source pixels that can be captured on a vertical active line. 9:0 vert_reload vertical line counter reload value. v ideo i nput s ubsystem buffer management hardware btv2115 brook t ree 259 bt in a similar fashion, the btv2811a s horizontal timing loop can shift the hori- zontal active to acquire good pixels in fast forward/reverse. the exact number of pixels to transfer per line is set by the other ?lds in the init structure. these ?lds allow for detection of loss of video lock horizontally and guarantee that only the anticipated amount of memory will be loaded by a control structure, i.e. a badly formatted video source cannot unintentionally overwrite vram registers. capture control structure de?ition the capture structure consists of three dwords of vram (dword0, dword1, dword2) as de?ed in table 146, table 147, and table 148. table 146. capture control structure dword0 (1 of 2) bit(s) field name description 31 end_of_list 0 = process the next sequential control structure. 1= this is the last control structure in the list. find the next one to process by following the video address register pointer. 30 set video interrupt 1=set the video interrupt ?g at the end of processing this control structure. 29 pause 0= continue video list processing at end of processing this structure. 1= reset the enable_video bit, vcr[7] at the end of processing this structure and after all data has been stored in vram. 28:27 format 00= 4:2:2 01= 4:1:1 10= mono (y only) 11= 4 to 1 decimation of 4:2:2 26 scan 0= even ?ld only 1= odd ?ld only 25 drop 0= normal operation, write to vram 1= drop this ?ld 24 chroma_mode pci-bus only 1 = enable chroma keying on luminance lsb (see ?arallel decoder interface? on page 266) 0= pass lsb y through to btv2487 23 v2 select enable 0= no change in buffer selection 1= dword0[21] selects video 2 a/b buffer v ideo i nput s ubsystem buffer management hardware btv2115 brook t ree 260 bt the starting vertical line ?ld is compared to the current vertical line in the current input video ?ld. if the ?ld is the correct type (odd or even), all lines after the speci?d vertical line are captured until the number of lines speci?d in the vertical line extent ?ld is captured or until vertical reset. conse- quently, care must be taken when starting capture after reset. the ?st structure in the capture list may cause incorrect data to be captured if the btv2115 starts cap- turing data at a location other than the beginning of the incoming video ?ld. to avoid this problem, set the ?st capture structure to drop an entire ?ld. valid cap- ture will then start in the second capture control structure. 22 v1 select enable 0= no change in buffer selection 1= dword0[20] selects video 1 a/b buffer 21 v2select 0= video 2 use buffer a for next frame 1= video 2 use buffer b for next frame 20 v1select 0= video1 use buffer a for next frame 1= video 1 use buffer b for next frame 19:10 reserved 9:0 starting vertical line matched against byte stream decoder ver- tical line counter to determine when to start data transfer for this control struc- ture. table 147. capture control structure dword1 bit(s) field name description 31:29 reserved 28:11 dword line pitch number of dwords to add to address of start of line capture. the 2 lsbs of this address must be zero, i.e., this pointer must point to a 4 dword (16 byte) aligned location in vram. 10 reserved 9:0 vertical line extent number of vertical lines to be transferred by the control structure table 146. capture control structure dword0 (2 of 2) bit(s) field name description v ideo i nput s ubsystem buffer management hardware btv2115 brook t ree 261 bt table 148. capture control structure dword2 bit(s) field name description 31:22 tag this tag ?ld is visible in the video address register when this control struc- ture is being processed. 21:2 mbus address vram dword address pointer to location in vram to store data captured by this control structure. the 2 lsbs of this address must be zero, i.e., this pointer must point to a 4 dword (16 byte) aligned location in vram. 1:0 reserved v ideo i nput s ubsystem line numbering system btv2115 brook t ree 262 bt line numbering system the btv2811a has a horizontal and vertical scaling mechanism. lines that are decimated must still be processed by the btv2811a so lines coming to the btv2115 are marked as either present or not. the marking is done by withholding the start of active pixels from lines that are discarded. the btv2115 video input subsystem counts only active lines. thus the line numbering system used in the control structures is based on a post scale count not the actual ntsc or pal line number. the btv2811a only scales vertically inside the active vertical region of the vid- eo frame. consequently, all lines in the inactive region are presented (and counted) by the btv2115. this ensures that the closed caption data will always be available, independent of the scaling set in the btv2811a. the btv2811a scales horizontally on all lines. therefore be sure to account for horizontal scaling in closed caption decoding. horizontal pixel counts within the btv2115 are post scaled pixel counts. v ideo i nput s ubsystem live video input btv2115 brook t ree 263 bt live video input before performing video capture, the following tasks must be performed: the btv2811a must be queried and initialized via the i 2 c bus. the control structure list is set up in vram the video address register is initialized to point to the control list struc- ture. the clock select bit in vcr[6] is set so that the btv2811a clock is used for capture. the video enable bit in vcr[7] is set so that the video capture logic will come out of reset and begin processing the structure list. for normal live video operation, the pause bit should not be set in any control structure. in order to display a cif resolution live video window, set up a control structure list with an init structure and two control structures. the ?st control structure (dword0) is set to wait for the even ?ld and is set to drop the video. the second control structure (dword1) is setup to wait for the odd ?ld vertical line 32 with a mode 4:1:1 format. the mbus address in this structure points to the ?st dword of the target buffer for the video image. the vertical line extent is set for 240 lines. the word line pitch ?ld is set to add the number of dwords per line to the starting address of each line. in this simple case, no double buffering is used so the vcr register should be set so that it controls the video a/b selection for the pacdac controller. to capture two ?lds, the ?st control structure (dword0) is set to capture the odd ?ld and points to the ?st scan line of the frame buffer. the second control structure (dword1) is set to capture even ?lds and points to the second line of the buffer. the word line pitch of both control structure is set to twice the number of dwords per scan line. v ideo i nput s ubsystem closed captioning capture with a video icon btv2115 brook t ree 264 bt closed captioning capture with a video icon a large video control structure list and a very small amount of buffer can be used to decode closed captioning while the video window is iconi?d. to implement this case, set up the list to process 30 separate ntsc frames and mark the last con- trol structure to interrupt the cpu and continue. each frame is processed by a set of two control structures (3 dwords in each structure). the ?st structure grabs the closed captioning line by being setup for the odd ?ld line 11 with a format of ?ono?so that only the y values are grabbed into a buffer. the second structure is setup to grab an iconi?d version of the video into a single small buffer. this structure s format is set to a 4 to 1 decimation of 4:2:2. each closed captioning structure points to a different line buffer while each icon structure points to the same video buffer. thus the cpu will be interrupted once per second to process an entire second s worth of closed captioning information. this requires approximately 181 dwords to hold the structure list, 4k dwords to hold the close captioning and 256 dwords to hold the video icon. to allow for interrupt latency in the cpu, set the actual structures to capture in a double-buffered fashion with two one second sequences of video captioning so that software can ping pong back and forth ( i.e., capture 60 frames worth). set the tag values of the ?st 30 frames in the control structures to 01h; and set the tags of the second 30 frames to 02h. thus, allowing software to quickly and easily tell which second s worth of close capturing is currently being processed. v ideo i nput s ubsystem single frame record example btv2115 brook t ree 265 bt single frame record example to simplify single frame capture, set the pause and interrupt bits in the last control structure element. upon completion of the list, the video control structure list processor will stop and an interrupt will be generated to the cpu. a more complicated example includes both a live video window loop and a cap- ture list. the live video loop occurs ?st in the control structure list with the end_of_list bit set in the last structure. as video is captured into the live win- dow video buffer, it encounters this eol bit and restarts at the top. if the application builds two control structure extensions immediately after the live window portion, the capture part is set to capture full resolution for both ?lds with its last control structure marked as interrupt and pause. thus, when the application is instructed to grab a single frame, it turns off the end_of_list bit in the last control structure of the live video window and waits for the interrupt to indicate completion of the capture. with this strategy, the live video that is cap- tured is a fresh, full time coherent frame. v ideo i nput s ubsystem parallel decoder interface btv2115 brook t ree 266 bt parallel decoder interface for pci-bus con?urations, the btv2115 can optionally use an alternate decode interface instead of the btv2811a videostream decoder. this option is enabled with bit 2 of the aud_vcr register; see table 141 on page 256. below, table 149 shows the corresponding signals between the btv2115 and the btv2811a and a parallel decoder interface. refer to figure 51 for a visual rep- resentation of the reference signals used for a scaling window. when using the video capture parallel interface, the video module can t deter- mine the difference between vertically blanked and non-blanked signals, except when using the bytestream interface. to work around this limitation (say, to cap- ture teletext or close-caption data), program the device generating the parallel vid- eo data to send the vertically blanked lines at the start of the frame. then use an appropriate video structure to capture/step-over this information. while in this mode, the video module refers to only the blank_src_pixels ?ld of the init structure (see table 145 on page 258). the active_src_pixels ?ld has no effect. table 149. parallel decoder interface btv2115 pin signals description btv2811a 8-bit interface ( pci- or vl-bus) parallel interface (pci-bus only) mm_data[7:0] luminance input signals vd[15:8] luma_data mm_data[15:8] chrominance input signals a. n/a chroma_data mm_data[16] pixel quali?r input signal to indicate active pixels of a quali?d line n/a pixel_q mm_data[17] line quali?r input signal to indicate active video phase n/a line_q mm_data[18] delay compensated horizontal reference sig- nal n/a href mm_data[19] vertical sync signal related to scalar input n/a vref mm_data[20] horizontal gate signal, a 1 indicates horizontal direction n/a gate_horz mm_data[21] reserved mm_data[22] vram input odd/even bit according to the internal ?ld processing n/a oe_field mm_data[23] keying signal of the chroma keyer n/a alpha a. chroma keying is enabled with bit 24 of vram dword0; see table 146 on page 259. v ideo i nput s ubsystem parallel decoder interface btv2115 brook t ree 267 bt figure 51. reference signals for scaling window video frame scaling f alling edge video frame scaling window pixel_q line_q href line_q gate_horz window cropped image scaled to 1/2 size pixel_q vref gate_horz line_q f alling edge href v ideo i nput s ubsystem parallel decoder interface btv2115 brook t ree 268 bt signal de?itions the video parallel interface signals are de?ed below. mm_data[ 7:0] ?luma_data mm_data[15:8] ?chroma_data the ?st pixel on a line is a cb pixel. every second pixel is a cr or cb pixel. the video module keeps track of cr and cb pixels by counting pixels from the ?st pixel on a line. mm_data[16] ?pixel_q mm_data[17] ?line_q video data is captured from the luma_data and chroma_data inputs on the rising edge of mm_clk during cycles when both quali?r inputs (pixel_q and line_q) are asserted (active high). if only one quali?r input is needed, then the line_q should be tied off to a logic 1. mm_data[18] ?href href rising edge is used to detect the start of a new line. this rising edge of this signal is only valid when line_q is asserted. this rising edge must also occur at least two clocks before the ?st pixel on the video line. href falling edge is used to reset the cr/cb pixel counter to expect a cb pixel at the start of the next line. mm_data[19] ?vref vref is used to reset the line count to zero at the start of a ?ld. this signal is active high and should be asserted for a short while at the start of every ?ld. mm_data[20] ?gate_horz gate_horz falling edge is used to detect the end of the video line which causes the video fifo to be ?shed and the address pointers to increment to the next line address in preparation for the next video line to be captured. this signal falling edge must occur as quickly as possible after the end of the video data on any video line to allow enough time for the video fifo to be ?shed into vram and possibly a new video control structure read from vram before the start of active video on the next line. standard ntsc/pal/secam video timing allows suf? cient completion time; for non-standard methods, contact brooktree for support. href and gate_horz are two separate signals with different but similar meanings. href is equivalent to a hreset signal that is used for counting video lines; it should see a rising edge as early as possible in the video line. gate_horz is equivalent to an active signal that should be asserted and deas- serted as quickly as possible before and after the active pixels on a line. if there is v ideo i nput s ubsystem parallel decoder interface btv2115 brook t ree 269 bt only one href/gate_horz type signal and it satis?s the timing requirements of both of these signals (rising edge as early as possible in the video line but at least two clocks before the ?st pixel and falling edge as soon as possible after the last active pixel), then both inputs can be tied together. mm_data[22] ?oe_field the oe_field bit is used to indicate the odd/even ?ld of the video being cap- tured: low for even ?ld, high for odd ?ld. mm_data[23] ?alpha the alpha bit is muxed into the least signi?ant bit of the luma data when the video capture logic is programmed to the alpha keying capture mode. note that this bit is subsampled by two; it is only sampled for cb (even) pixels but is stored in the luma lsb for both the cb and corresponding cr pixel. video interface timing figure 52 provides the video interface timing diagram. bytestream and parallel video interface timing: t setup = 5.0ns before mm_clk rising edge t hold = 4.0ns after mm_clk rising edge figure 52. video interface timing diagram valid input data t setup t hold mm_clk mm_data[23:0] brook t ree 271 bt a udio i nterface introduction the btv chip set provides a completely self-contained audio subsystem for mi- crosoft windows 3.1, windows 95, and nt, as well as supports compatibility with the many dos-based games. in addition, the btv2115 provides a gateway to and from the consumer electronics world of digital audio via the aes/ebu (audio en- gineering society/european broadcasting union) serial audio input and output pins. figure 53 shows a typical audio system con?uration. figure 53. typical audio system con?uration sa_out sa_in f-o r cvr f-o x mit fiber optic fiber optic b t v2115 b t v2300 aes_out line i n mic i n line o ut cd a nalog i n opl i nput d igital a udio d evice a udio i nterface aes/ebu format btv2115 brook t ree 272 bt aes/ebu format understanding the aes protocol is fundamental to understanding the btv audio components, therefore a brief description is in order. the block-oriented protocol is transmitted at 128 times the sample clock (i.e. 6.144 mhz for 48 khz samples) in a self-clocking (manchester/bi-phase mark), block-oriented protocol with synchronization. since the btv2115 is over-sam- pling this signal for decode, it will accommodate the full gamut of audio sample rates. support of parity, validity, user or channel status is not needed for implemen- tation within the btv2300 s the serial encoder (but, is required for external com- munications). the block-oriented protocol consists of a series of frames. each frame consists of two channel subframes, 32-bits each, as shown in figure 54. the rate of trans- mission of each frame corresponds to the source sampling frequency. that is, the clock corresponding to each bit time within a frame is equal to 64 times the sample clock. the manchester encoding brings the basic encoder clock rate to 128 times the sample rate. figure 54 shows that each subframe contains one 20 bit audio sample for either the left or right channel, a 4 bit sync or preamble ?ld, a 4 bit aux- iliary audio ?ld and 4 one bit ?lds (de?ed below). the btv2115 always transmits 2-channel 16 bit stereo data, even when the source material is mono (in which case it is duplicated on both left and right chan- nels). both the channel status block and the user block are identical for each chan- nel. the 16 bit sample is msb justi?d within the 20 bit audio ?ld of a frame. the 20 bit samples are sent lsb ?st in twos complement notation. frames are sent in blocks of from 5 to 256 frames. the block length is pro- grammed via the aud_ebl register. for communicating solely with the btv2300 audio chip, the block length is arbitrary (but the shorter the block length, the lower the btv2300 register update latency). when communicating with an aes/spdif device (e.g. a minidisc), the block length should be set for exactly 192 frames by loading 191 (bfh) into the block length register. notice that each frame in figure 54 contains 8 bits of ?ux?data, four from the left subframe and four from the right subframe. when communicating with the btv2300, each frame contains one byte of data going to or from the btv2300. the byte associated with the ?st frame of a block to the btv2300 contains the register address. the ?st frame of a block is marked with a unique sync or preamble ?ld that indicates both start of block and left frame, see figure 54. the usage of the aux bits will be de?ed in more detail below. a udio i nterface aes/ebu format btv2115 brook t ree 273 bt the four one-bit ?lds are used in two ways. two of the ?lds, v and p, have meaning on a subframe basis only. the validity bit, v, is used to mark each audio sample as valid or invalid (present or not present) with zero indicating valid. parity bit, p, is used to send even parity for the subframe. the u and c bits are used in a very different way. each represents a 1-bit serial channel of data running at a rate of 1 bit per audio sample. thus, for 48khz cd au- dio, there are 48kbits of left user data, 48kbits of right user data, 48kbits of left channel data and 48kbits of right channel data per second. figure 54. aes framing s ync l s b m s b l s b m s b vucp 4 4 20 1111 a udio d ata a uxiliary d ata s ample v alidity u ser b it d ata c hannel s tatus s ubframe p arity (s tart ) lrlr lr (s tart ) l r 1 1 192 1 1 192 22 s ample f req . l eft s ubframe s ync r ight s ubframe s ync l eft s ubframe s ync p lus b lock s tart b lock f rame a udio i nterface aes/ebu format btv2115 brook t ree 274 bt v = validity (0 = valid) u = user data, 1 bit c = channel data, 1 bit p = parity (generates even), 1 bit notice that the block start preamble is used to mark the beginning of user and channel bit streams so that in 192 frame blocks, there are 24 bytes of each bit stream per block. the btv chip set does not use the user and channel bit streams for communication. however, the btv2115 can generate or store user and chan- nel data when communicating with an aes/spdif consumer/professional audio device. see ?hannel status?on page 313 for a discussion of the btv2300 channel stream versus that generated for external audio components. figure 55 de?es the aes timing. figure 55. aes timing diagram 01 0 0 1 1 t t = 1/(sf x 128) sf = sample frequency 2t data block 0 0 1 or left right or or (left) a udio i nterface aes/ebu format btv2115 brook t ree 275 bt aes references aes recommended practice for digital audio engineering -- serial transmission format for linearly represented digital audio data , aes3-1985 (ansi s4.40- 1985); audio engineering society, inc., 60 east 42nd street, new york, new york 10165, usa john watkinson, the art of digital audio , 1991, focal press. clif sanchez and roger taylor, overview of digital audio interface data struc- tures ; crystal semiconductor corporation application note, from volume 1 data book, april 1992 digital audio interface , eiaj cp-340, september 1987. a udio i nterface audio subsystem btv2115 brook t ree 276 bt audio subsystem figure 56 shows a block diagram of the btv2115 audio subsystem. the btv2115 provides two aes outputs. the serial audio out port (sa_out) is connected directly to the btv2300, and aes_out is routed through a digital audio device (as shown in figure 53). the two streams must be separated since btv2300 control data is transmitted in the aes aux ?ld and arbitrary user data is transmitted in the aux ?ld for consumer audio data. the audio subsystem contains one aes encoder (recall that the aes stream is manchester encoded). consequently, the btv2115 contains a ?ull aes encod- er?which transmits a continuous stream of ones to quiesce either the consumer de- vice or the btv2300 when it is not being driven by the aes encoder. typically the serial audio input (sa_in) receives an aes stream from the btv2300. note that the btv2300 has an integrated mux which can pass a consum- er device s aes stream through the btv2300 if desired. the sa_in line goes through a diagnostic wrap mux into the aes decoder. the aes decoder always runs on clk25 which provides suf?ient over-sam- pling to reliably decode the aes bit stream at up to a 48 khz stereo audio sample rate. the aes encoder receives the serial audio stream and offers a parallel inter- face to the rest of the btv2115 audio subsystem. the aes encoder receives a sample rate times 128 clock, derived either from clk17 or clk25. the aes encoder offers a parallel interface to the rest of the btv2115 audio subsystem and generates the serial audio stream. aclk is output to the audiostream interface via the audclk_out signal pin. a udio i nterface audio subsystem btv2115 brook t ree 277 bt figure 56. btv2115 audio subsystem block diagram l egacy a udio e mulation a udio r egisters h ost b us v ertical i 2 c v ideo r egister c opy l ogic opl m emory b us m emory c ontroller m edia irq clk25 clk17 s ample c lock aes e ncoder clk25 a udio p rocessing u nit a udio m emory i nterface aes f ormatting aes d ecoder n ull aes 2:1 3:1 2:1 aes_out sa_out sa_in 32 i nterrupt l ogic b uffer aclk a udio i nterface audio subsystem btv2115 brook t ree 278 bt all of the btv2300 registers are read/written via the aux ?ld of the aes streams. btv2300 registers are written by sending a start address in the ?st byte of the aux block as marked by the start block preamble of the aes frame. subse- quent bytes within the aux stream are treated as data and are written to btv2300 registers for each successive aes frame. the register address in both the btv2300 and the btv2115 auto-increments for each data byte sent. the address register does not wrap. instead, it stops at the highest address and subsequent data bytes are ignored. the registers within the btv2300 are write-only. there is no mechanism for the btv2115 to read back btv2300 register data. however, the btv2300 registers are ?hadowed?within the btv2115 so that software can read the last value written to the btv2300. the btv2115 reads two registers from the btv2300 via the sa_in stream: the btv2300 chip id register (cid) which contains a version/revision code and the btv2300 application interface. the ?st byte of a block from the btv2300 con- tains the cid while the second and subsequent blocks of aux data from the btv2300 contain samples of the application interface. the application interface is bidirectional. the btv2300 application direction register contains bit by bit controls of the direction of the application interface; one means output, zero means input. data written to the btv2115 application register (app_wr) is transmitted to the btv2300 for possible output on the applications interface, subject to the direction register mask. the register copy logic block in figure 56 is responsible for watching the data written to the bank of btv2300 shadow registers so that an appropriate address can be generated at the start of the next block of aes output data. the register copy block keeps track of the lowest register written but not yet transmitted. on each block, the register transfer will begin with the lowest modi?d btv2300 shadow register. btv2300 register bytes are assembled from left and right subframes, as shown in table 150. table 150. btv2300 register to aux mapping aes aux btv2300 data bit right_aux[3] bit[7] right_aux[2] bit[6] right_aux[1] bit[5] right_aux[0] bit[4] left_aux[3] bit[3] left_aux[2] bit[2] left_aux[1] bit[1] left_aux[0] bit[0] a udio i nterface audio subsystem btv2115 brook t ree 279 bt the aes formatter manages the construction of blocks and supplies frame level parallel data to the encoder and receives it from the decoder. with the exception of passing btv2300 shadowed register values into the aes stream and copying the btv2300 cid and application read data into the btv2115 audio registers, all data in the aes streams is zero or is copied directly to or from media buffer. when not using the media buffer for the aes ?ucb?components (see ?udio data for- mats in the media buffer?on page 283), a consumer format digital audio stream is generated. however, when the media buffer is used as a source or destination for channel status and user data, a professional format digital audio stream may be uti- lized. digital signal processing is performed within the audio processing unit (apu); refer to figure 57. this consists of format conversion into stereo 16-bit 2 s complement audio samples, ?ating point multiplies to perform gain or attenua- tion, clipping detection, maximum value holds, and sample summation. the btv2115 audio system supports two simultaneous audio streams. each ste- reo stream permits either playback or record, thus allowing two stereo playback streams to the btv2300. the apu contains a digital mixer that can be used to blend both left streams together and both right streams together. the output of the aes decoder is always available for mixing with the playback data stream, even if neither of the audio streams is set up for recording. the apu can provide decompression of various pcm and adpcm formats as summarized in table 153 through table 163. the apu provides other services such as peak value detection and an average value accumulation. a udio i nterface audio subsystem btv2115 brook t ree 280 bt figure 57. audio processing unit a udio m emory i nterface l r f ormat c onvert g ain or a ttenuation l r f ormat c onvert g ain or a ttenuation g ain or a ttenuation g ain or a ttenuation m eter m eter l eft r ight m eter m eter l eft r ight g ain or a ttenuation g ain or a ttenuation f ormat c onvert l r a udio i nterface audio subsystem btv2115 brook t ree 281 bt in addition to handling fetching or storing of the two stereo streams, the audio memory interface (ami) is responsible for fetching, following and executing the audio structure list (as shown in figure 58). each structure element in the media buffer belongs either to the primary list or the secondary list. the ?st structure in the primary list is pointed to by the primary structure address register. similarly the ?st structure in the secondary list is pointed to by the secondary structure address register. all structure elements consist of two dwords in the format shown in table 151 and table 152. figure 58. stream and data structure stream address struc 0 struc 1 struc n-1 l packet 0 packet n-1 media buffer audio samples audio samples register dword0 dword1 dword1 dword0 dword0 dword1 a udio i nterface audio subsystem btv2115 brook t ree 282 bt table 151. audio structure dword 0 bit field description 31 last 1= go to top of structure list as desig- nated by address in register 0 = use next 2 dwords to continue 30 interrupt 1= generate interrupt when number of samples goes to zero 0= no interrupt 29:26 0 reserved (set to zero). 25 silence 1 = set samples to zero, ignoring data 0 = normal, use data 24:23 mode 00= stereo 01=mono,only left channel 10=mono, only right channel 11=mono, both channels mono puts mono source data on both channels for playback. for record, con- verts stereo source data to mono 22:19 structure_id structure id for application use 18:16 0 reserved (set to zero) 15:0 number_samples number of samples to playback or record in the speci?d format and mode a udio i nterface audio subsystem btv2115 brook t ree 283 bt audio data formats in the media buffer in all stereo modes, the even samples contain left data and the odd samples contain right data. in all 16-bit formats, the data is represented as a 2 s complement integer, and the sign bit is the most signi?ant bit of the most signi?ant byte, in little en- dian style. in all 8-bit pcm formats, the data is represented as an unsigned integer. the vucb format contains the same valid, user, and channel status bits as the vucp format described in ?es/ebu format?on page 272. the b bit indicates block boundaries (instead of parity, which is generated within the encoder). for record operations, the b bit is set on both left and right vucb samples at the block boundary. for playback, the b bit is used to mark the beginning of a new serial au- dio block. note that if the playback format incorporates aux, and the serial data stream is routed to the btv2300 (as opposed to a null stream), all btv2300 register programming is assumed by that media buffer packet and care should be taken to avoid unexpected results. table 152. audio structure dword 1 bit field description 31 0 reserved (set to zero) 30:29 fb_format 00= data only 01= data+aux+vucb 10=vucb only 11= aux+vucb 28 adpcm_ref 1 = if the data format is adpcm then this packet contains a refer- ence byte as ?st sample 0 = no reference byte 27:25 data_format 000= 16-bit pcm 001= 8-bit pcm 010 = reserved 011 = reserved 100 = reserved 101 = 4-bit adpcm ? 110 = 2.6-bit adpcm ? 111 = 2-bit adpcm ? 24 playback 1= playback 0 = record 23:20 0 reserved (set to zero) 19:0 data_address dword media buffer address of data for this structure ? only for playback (not record) a udio i nterface audio subsystem btv2115 brook t ree 284 bt the primary and secondary streams are completely independent. both may be used to play into a single stream. for example, primary may be used for data-only (in one of various formats) while secondary may be used in vucb format, in which case both streams are merged in the apu. also, data-only formats from both streams of different types are also merged within the apu. table 153 through table 163 show the decompression of various pcm and ad- pcm formats. table 153. 16-bit format bit field description 31:16 sample 1 sample 1 15:0 sample 0 sample 0 table 154. 8-bit format bit field description 31:24 sample 3 sample 3 23:16 sample 2 sample 2 15:8 sample 1 sample 1 7:0 sample 0 sample 0 table 155. 4-bit adpcm format with reference bit field only mono supported 31:28 sample 5 27:24 sample 6 23:20 sample 3 19:16 sample 4 15:12 sample 1 11:8 sample 2 7:0 sample 0 is a reference pcm byte. a udio i nterface audio subsystem btv2115 brook t ree 285 bt table 156. 4-bit adpcm format bit field only mono supported 31:28 sample 6 27:24 sample 7 23:20 sample 4 19:16 sample 5 15:12 sample 2 11:8 sample 3 7:4 sample 0 3:0 sample 1 table 157. 2.6-bit adpcm format with reference bit field only mono supported 31:29 sample 7 28:26 sample 8 25:24 sample 9 23:21 sample 4 20:18 sample 5 17:16 sample 6 15:13 sample 1 12:10 sample 2 9:8 sample 3 7:0 sample 0 is a reference pcm byte. a udio i nterface audio subsystem btv2115 brook t ree 286 bt table 158. 2.6-bit adpcm bit field only mono supported 31:29 sample 9 28:26 sample 10 25:24 sample 11 23:21 sample 6 20:18 sample 7 17:16 sample 8 15:13 sample 3 12:10 sample 4 9:8 sample 5 7:5 sample 0 4:2 sample 1 1:0 sample 2 table 159. 2-bit adpcm format with reference bit field only mono supported 31:30 sample 9 29:28 sample 10 27:26 sample 11 25:24 sample 12 23:22 sample 5 21:20 sample 6 19:18 sample 7 17:16 sample 8 15:14 sample 1 13:12 sample 2 11;10 sample 3 9:8 sample 4 7:0 sample 0 is a reference pcm byte. a udio i nterface audio subsystem btv2115 brook t ree 287 bt table 160. 2-bit adpcm format bit field only mono supported 31:30 sample 12 29:28 sample 13 27:26 sample 14 25:24 sample 15 23:22 sample 8 21:20 sample 9 19:18 sample 10 17:16 sample 11 15:14 sample 4 13:12 sample 5 11;10 sample 6 9:8 sample 7 7:6 sample 0 5:4 sample 1 3:2 sample 2 1:0 sample 3 table 161. vucb only format bit field 31:28 vucb 7 27:24 vucb 6 23:20 vucb 5 19:16 vucb 4 15:12 vucb 3 11:8 vucb 2 7:4 vucb 1 3:0 vucb 0 a udio i nterface audio subsystem btv2115 brook t ree 288 bt table 162. aux+vucb format bit field 31:28 vucb 3 27:24 aux 3 23:20 vucb 2 19:16 aux 2 15:12 vucb 1 11:8 aux 1 7:4 vucb 0 3:0 aux 0 table 163. data+aux+vucb format bit field 31:28 vucb 0 27:24 aux 0 23:16 set to zero 15:0 data sample 0 a udio i nterface audio registers btv2115 brook t ree 289 bt audio registers the audio registers are memory mapped and are accessible from either the protect- ed mode aperture or the real mode aperture, see ?rotected mode aperture?on page 101 and ?eal mode aperture?on page 127. although 1mb of audio space is reserved in the protected mode aperture only 1024 bytes are used. two lsbs of the address are encoded in the byte enables. only 8 of the remaining bits are actually decoded to yield 256 dwords of audio reg- ister space. these 256 dwords alias repeatedly through the 1mb of protected mode space reserved for audio. unless speci?d otherwise, all audio registers are set to zero at reset. all reserved bits return zero when read, and should be written with zero to maintain compatibility with future versions or revisions of the device. table 164 summarizes the audio registers. table 164. audio address map (1 of 3) register address name description 00500000 aud_isr interrupt status 00500002 aud_imr interrupt mask 00500004 aud_istr interrupt state 00500006 aud_appr application port read data 00500007 aud_cid codec id 00500008 aud_sdcr serial data control 00500009 aud_ebl encoder block length 0050000a aud_ebp encoder block position 0050000b aud_dsr decoder status 00500010 aud_ch0 channel status byte 0 00500011 aud_ch1 channel status byte 1 00500012 aud_ch2 channel status byte 2 00500013 aud_ch3 channel status byte 3 00500040 aud_psa primary stream address 00500044 aud_psc primary stream counter 00500048 aud_ssa secondary stream address 0050004c aud_ssc secondary stream counter 00500050 aud_pll primary left level a udio i nterface audio registers btv2115 brook t ree 290 bt 00500052 aud_prl primary right level 00500054 aud_sll secondary left level 00500056 aud_srl secondary right level 00500058 aud_rmll record monitor left level 0050005a aud_rmrl record monitor right level 0050005c aud_ns number summed register 00500060 aud_lpsum left playback sum 00500062 aud_rpsum right playback sum 00500064 aud_lpmax left playback max. 00500066 aud_rpmax right playback max. 00500068 aud_lrsum left record sum 0050006a aud_rrsum right record sum 0050006c aud_lrmax left record max. 0050006e aud_rrmax right record max. 005000bc aud_car codec address 005000c0 aud_clk clock 005000c2 aud_fclk filter clock divisor 005000c3 aud_cmode codec mode 005000c4 aud_appo application port direction 005000c5 aud_appd application port write data 005000c6 aud_mix mixer control 005000c7 aud_mux mux selector 005000c8 aud_cdl cd left attenuation 005000c9 aud_cdr cd right attenuation 005000ca aud_ll line left attenuation 005000cb aud_lr line right attenuation 005000cc aud_fml fm left attenuation 005000cd aud_fmr fm right attenuation table 164. audio address map (2 of 3) register address name description a udio i nterface audio registers btv2115 brook t ree 291 bt interrupt status register name: aud_isr address: gbase | 00500000h, read/write size: 16 bit on read, this register indicates the active/inactive state for each in- terrupt. the actual interrupt to the bus is a reduction of the interrupt sta- tus register by a logical or. the interrupt state register is bit-wise anded with the interrupt mask register to generate the status register. interrupt status bit de?itions are as shown in table 165. a type of ?vent?means that the interrupt occurs on the leading edge of the event and will remain until cleared by writing to either the interrupt status or state register. a type of ?evel?means that the value of the interrupt is passed through (using the mask) and must be reset via some other mechanism, e.g. the vga vertical interval interrupt mechanism. writing a 1 to individual bits of the status register will re- set that particular interrupt, if it is of type ?vent. 005000ce aud_micl mic left gain 005000cf aud_micr mic right gain 005000d0 aud_dacl dac left attenuation 005000d1 aud_dacr dac right attenuation table 165. interrupt status, state and mask register bits (1 of 2) bit field type description 15 la_command_int event legacy audio command (event) 14 la_pro_write_int event legacy audio pro write command (event) 13 primary_int event audio primary structure requested irq (event). 12 secondary_int event audio secondary structure requested irq (event) 11 iic_master_int level i 2 c master controller irq (level) 10 iic_slave _ int level i 2 c slave controller irq (level) 9 video_capture_int event video input subsystem, structure requesting irq (event) 8 vga_retrace_int level vga or pdc requesting irq (level) 7 external_int level from an on-board external device table 164. audio address map (3 of 3) register address name description a udio i nterface audio registers btv2115 brook t ree 292 bt interrupt mask register name: aud_imr address: gbase | 00500002h, read/write size: 16 bit function: this read/write register contains a bit-for-bit mask for each interrupt source. 1 = enable the corresponding interrupt. 0 = mask off the corre- sponding interrupt type. the contents of this register are bit-wise anded with the interrupt state register bits to form the interrupt status register and to generate a request to the cpu bus. refer to table 165 for a mapping of interrupt types to bit positions for this register. reserved interrupts cannot be masked. interrupt state register name: aud_istr address: gbase | 00500004h, read/write size: 16 bit function: this read/write register contains the storage elements for interrupt types that are ?gged as events. interrupt types that are ?gged as lev- els do not actually have a storage element here but are passed through as if they were in this register. the contents of this register are bit-wise anded with the interrupt mask register bits to present an interrupt re- quest to the cpu bus. writing a 1 to individual bits of the state register will reset that particular interrupt type in the interrupt status register, if it is of type ?vent. refer to table 165 for a mapping of interrupt types to bit positions for this register. 6:5 reserved n/a reserved 4 aes_decoder_int event aes decoder went into lock, or went out of lock (event) 3 audio_clipped event audio signal was clipped; examine metering registers to determine which channel/direction (event) 2:0 reserved n/a reserved table 165. interrupt status, state and mask register bits (2 of 2) bit field type description a udio i nterface audio registers btv2115 brook t ree 293 bt application port read data register name: aud_appr address: gbase | 00500006h, read only size: 8 bit function: this read only register provides an access port for software to read the state of the btv2300 applications port. when the corresponding bit in aud_appo is a zero, the value applied externally to the btv2300 ap- plications port pin can be read here by software. the applications port write data is in aud_appd. for this register to be valid, aud_sdcr loopback (see table 167) must be set to normal and the aes decoder must be locked (see table 165) and have read at least two frames. btv2300 chip id register name: aud_cid address: gbase | 00500007h, read only size: 8 bit function: this read only register returns the chip id information of the btv2300. in addition, it returns a status bit indicating when the circuitry in the btv2300 is undergoing recalibration. after reset, this register is not valid until the decoder is locked (see table 165) and the ?st frame has been read. aud_sdcr loopback (see table 167) must be set to normal. bit de?itions are shown in table 166. serial data control register name: aud_sdcr address: gbase | 00500008h, read/write size: 8 bit function: this register controls various global aspects of the serial data stream, including which serial output pin is driven by the aes encoder and which is driven by the null encoder. refer to table 167. this register defaults to 08h (loopback sa_out). table 166. aud_cid btv2300 chip id register bit field description 7:4 major_id [4:0] = 0h is major id 3:1 minor_id [4:0] = 4h or greater 0 calib_status 1= btv2300 being recalibrated 0= calibration complete a udio i nterface audio registers btv2115 brook t ree 294 bt encoder block length register name: aud_ebl address: gbase | 00500009h, read/write size: 8 bit function: this register provides the encoder block length. set the block length to one less than the desired block length. for aes/spdif compatibility use 0bfh (191). after reset, aud_ebl is set to 4 for a block length of 5, which is the minimum block length for communicating with the btv2300. maximum block length is 256. (actual block length range is 5 to 256, while valid aud_ebl range is 4 to 255.) due to the way the btv2300 registers are shadowed and transmitted, the shorter the block length, the shorter the latency time on register changes. table 167. serial data control register bit field description 7 reserved reserved. 6 null_sa_out put nulls onto the sa_out pin which is connected to the btv2300 so that it will ignore the aes stream directed to a consumer device. 5 null_aes_out put nulls onto the aes_out pin which may be connected to con- sumer device so that it will ignore the aes stream directed to the btv2300. 4:3 loopback signal source for the decoder: 00= normal operation (sa_in) 01= loopback sa_out 10= loopback aes_out 11= reserved 2 disable_parity 1= disable parity checking in the aes decoder. 1 odd_parity_encoder 1= generate odd parity in the encoder 0 = generate even parity in the encoder 0 odd_parity_decoder 1= use odd parity in the encoder 0= use even parity in the encoder a udio i nterface audio registers btv2115 brook t ree 295 bt encoder block position register name: aud_ebp address: gbase | 0050000ah, read only size: 8 bit function: this diagnostic register shows the binary count of frames left within a block (i.e. it counts down from n-1 to zero, where n is the number of frames in a block). decoder status register name: aid_dsr address: gbase | 0050000bh, read only size: 8 bit function: this diagnostic and error recovery register provides information about the current status of the aes decoder. refer to table 168. reserved name: reserved address: gbase | 0050000ch size: 32 bit channel status byte 0 register name: aud_ch0 address: gbase | 00500010h, read only size: 8 bit function: this register contains the ?st byte of channel status data from the se- lected signal source selected (see table 167), as de?ed by aes/sp- dif (see table 198). channel status byte 1 register name: aud_ch1 address: gbase | 00500011h, read only size: 8 bit function: this register contains the second byte of channel status data from the selected signal source selected (see table 167), as de?ed by aes/sp- dif (see table 198). table 168. decoder status register bit field description 7 locked 1= decoder is locked to an incoming aes stream. 6 signal_present 1= decoder detects signal transitions on the selected input data stream. 5:0 reserved a udio i nterface audio registers btv2115 brook t ree 296 bt channel status byte 2 register name: aud_ch2 address: gbase | 00500012h, read only size: 8 bit function: this register contains the third byte of channel status data from the se- lected signal source selected (see table 167), as de?ed by aes/sp- dif (see table 198). channel status byte 3 register name: aud_ch3 address: gbase | 00500013h, read only size: 8 bit function: this register contains the fourth byte of channel status data from the selected signal source selected (see table 167), as de?ed by aes/sp- dif (see ?hannel status usage?on page 313). bytes 5 through 24 can only be determined by recording in a vucb mode. reserved name: reserved address: gbase | 00500014 through gbase | 0050003c size: 11 locations of 32 bits each primary stream address register name: aud_psa address: gbase | 00500040h, read/write size: 32 bit function: this register contains the media buffer address of the 1st control struc- ture associated with the primary stream, along with some control bits. refer to table 169. setting enable_primary to a zero will disable the processing of audio and control structure data. the transition of enable_primary from a 0 to a 1 will begin the processing of con- trol structure information beginning at the primary_address. setting pause_primary to a 1 will cause the primary audio stream to pause, holding the current value. processing of the stream data and control structures will continue when pause_primary is set to zero. the primary buffer counter (see ?ud_psc?on page 297) may be reset by setting enable_primary_counter to a 0. this bit must be set to a 1 to enable the fetching and processing of primary con- trol structures and data. a udio i nterface audio registers btv2115 brook t ree 297 bt primary stream counter register name: aud_psc address: gbase | 00500044h, read/write size: 32 bit function: this register provides read access to a number of status indicators for the primary stream. its main function is to support the semaphore counter which allows software to copy audio buffers to the media buff- er and easily mark the associated structure as available for processing. every time a write occurs to bits 31:24, the primary stream counter is incremented. every time hardware completes the processing of a struc- ture the counter is decremented until zero. the next structure in the list will not be fetched or processed unless the primary_counter is non-zero. refer to table 170. table 169. primary address register bits field description 31 enable_primary 1 = enable primary stream. 0 = disable primary stream. 30 pause_primary 1 = pause the processing of primary stream data. 0 = continue processing. 29 enable_primary_ counter 1 = count primary structures 0 = hold counter in reset sate 28:22 reserved 21:2 primary_address media buffer byte address of the ?st structure in the primary list. 1:0 always 0 (dword aligned) table 170. primary stream counter (1 of 2) bits field description 31:24 primary_counter primary stream counter is incremented by writes of any data value to this byte. counter is decremented when an audio structures and associated data has been processed. 23:20 primary_id read only ? 19 reserved 18 silence_primary read only ? a udio i nterface audio registers btv2115 brook t ree 298 bt secondary stream address register name: aud_ssa address: gbase | 00500048h, read/write size: 32 bit function: this register contains the media buffer address of the 1st control struc- ture associated with the secondary stream, along with some control bits. refer to table 171. setting enable_secondary to a zero will disable the process- ing of audio and control structure data. the transition of enable_secondary from a 0 to a 1 will begin the processing of control structure information beginning at the secondary_address. setting pause_secondary to a 1 will cause the secondary au- dio stream to pause, holding the current value. processing of the stream data and control structures will continue when pause_secondary is set to zero. the secondary buffer counter (see ?ud_ssc?on page 299) may be reset by setting enable_secondary_counter to a 0. this bit must be set to a 1 to enable the fetching and processing of secondary control structures and data. 17 primary_last read only ? 16 primary_irq read only ? 15:0 primary_length read only. shows number of samples left to process. range: 0 to n, where n = number of samples in the buffer. ? value taken from media buffer structure currently being processed or the last one completed, if stream is idle. table 171. secondary address register (1 of 2) bits field description 31 enable_secondary 1 = enable secondary stream. 0 = disable secondary stream. 30 pause_secondary 1 = pause the processing of sec- ondary stream data. 0 = continue processing table 170. primary stream counter (2 of 2) bits field description a udio i nterface audio registers btv2115 brook t ree 299 bt secondary stream counter register name: aud_ssc address: gbase | 0050004ch, read/write size: 32 bit function: this register provides read access to a number of status indicators for the secondary stream. its main function is to support the semaphore counter which allows software to copy audio buffers to the media buff- er and easily mark the associated structure as available for processing. every time a write occurs to bits 31:24, the secondary stream counter is incremented. every time hardware completes the processing of a structure the counter is decremented until zero. the next structure in the list will not be fetched or processed unless the secondary_counter is non-zero. refer to table 172. 29 enable_secondary_ counter 1= count secondary structures 0= hold counter in reset sate 28:22 reserved 21:2 secondary_address address of the ?st structure in the secondary list. 1:0 always zero (dword aligned). table 172. secondary stream counter bits field description 31:24 secondary_counter secondary stream counter is incre- mented by writes of any data value to this byte. counter is decremented as audio structures complete processing. 23:20 secondary_id read only ? 19 reserved 18 silence_secondary read only ? 17 secondary_last read only ? 16 reserved read only ? 15:0 secondary_length read only. shows number of samples left to process. range: 0 to n, where n = number of samples in the buffer. ? value taken from media buffer structure currently being processed or the last one completed, if stream is idle. table 171. secondary address register (2 of 2) bits field description a udio i nterface audio registers btv2115 brook t ree 300 bt level registers all level registers use 6-bit values to digitally control gain or attenuation over the range of +18.0 db to -75.0 db (including full mute) in 1.5 db steps. refer to table 173. note that applying gain may cause the signal to clip, which can be detected in bit 3 of the interrupt state (and potentially status) registers. refer to table 165 on page 291. primary level registers name: aud_pll, aud_prl address: gbase | 00500050h, read/write size: 32 bit function: this register controls the left and right audio signal level on the prima- ry playback stream, after format conversion and prior to being mixed with the secondary or record streams. refer to table 174. table 173. level register values bit[5:0] gain or attenuation 111111 +18.0 db 111110 +16.5 db ......... ......... 110100 +1.5 db 110011 0.0 db 110010 -1.5 db .......... .......... 000010 -73.5 db 000001 -75.0 db 000000 mute table 174. primary level registers bits field description 31:14 reserved 13:8 right_level values from table 173 7:6 reserved 5:0 left_level values from table 173 a udio i nterface audio registers btv2115 brook t ree 301 bt secondary level registers name: aud_sll, aud_srl address: gbase | 00500054h, read/write size: 32 bit function: this register controls the left and right audio signal level on the sec- ondary playback stream, after format conversion and prior to being mixed with the primary or record streams. refer to and table 175. record monitoring level registers name: aud_rmll, aud_rmrl address: gbase | 00500058h, read/write size: 32 bit function: these left and right record monitoring levels do not affect the data going to memory (if recording) and are only used for mixing the monitored record data into the playback stream for monitoring. the exception to this rule is when one of the streams is recording in the mode ?ono - both channels?(see table 151 on page 282). in this case, aud_rmll will affect both the monitor and record data. refer to table 176. number summed register name: aud_ns[1:0] address: gbase | 0050005ch, read only size: 32 bit function: the apu accumulates a per channel average of the sample values so that a ?uasi?power meter function can be implemented without bog- ging down the x86. it is the x86 s job to do the division to achieve a signal average value. this register provides the denominator for all channels in play and/or record mode and is reset when read. refer to table 177. table 175. secondary level registers bits field description 31:14 reserved 13:8 right_level values from table 173 7:6 reserved 5:0 left_level values from table 173 table 176. record monitoring levels bits field description 31:13 reserved 12:8 right_monitor values from table 173 7:6 reserved 5:0 left_monitor values from table 173 a udio i nterface audio registers btv2115 brook t ree 302 bt right/left playback sum registers name: aud_lpsum, aud_rpsum address: gbase | 00500060h, read only size: 32 bit function: the sum of playback samples is a 32-bit unsigned value and only the upper 16 bits are made available to software. thus a signi?ant number of samples must be accumulated before a meaningful average can be computed. all bits, including the least signi?ant bits which are not viewable are zeroed when read. refer to table 178. right/left playback max registers name: aud_lpmax, aud_rpmax address: gbase | 00500064h, read only size: 32 bit function: the apu implements a maximum absolute value function with the current maximum value of playback held in this register. this value is reset when read. refer to table 179. right/left record sum registers name: aud_lrsum, aud_rrsum address: gbase | 00500068h, read only size: 32 bit function: the sum of record samples is a 32-bit signed value and only the upper 16 bits are made available to software. thus a signi?ant number of samples must be accumulated before a meaningful average can be computed. all bits, including the least signi?ant bits which are not viewable, are zeroed when read. refer to table 180. table 177. number summed bit field description 31:16 reserved 15:0 number_summed increments at sample rate. cleared when read. table 178. playback sum registers bit field description 31:16 right_sum right playback sum. 15:0 left_sum left playback sum table 179. playback max registers bit field description 31:16 right_max right playback maximum (max value is 7fffh) 15:0 left_max left playback maximum (max value is 7fffh) a udio i nterface audio registers btv2115 brook t ree 303 bt right/left record max registers name: aud_lrmax, aud_rrmax address: gbase | 0050006ch, read only size: 32 bit function: the apu implements a maximum absolute value function with the current maximum value held in aud_lrmax and aud_rrmax. this value is reset when read. refer to table 181. legacy audio emulation registers name: la_emulation_registers address: gbase | 00500080h through gbase | 005000bbh size: 32-bit function: these registers are used to emulate the legacy audio function and are for internal purposes only. however, register 00500080h controls the legacy audio address decoder base address select (022xh when bit 6 = 0, 024xh when bit 6 = 1), as well as enabling of the legacy audio i/ o decoder (disabled when bit 7 = 0, enabled when bit 7 = 1). this reg- ister should be accessed in a read-modify-write manner. btv2300 address register name: aud_car address: gbase | 005000bch, read only size: 8 bit function: this register re?cts the current setting of the btv2300 address regis- ter and is used to track which btv2300 register is currently marked as the ?st one to be sent in the next aes block. table 180. record sum registers bit field description 31:16 right_sum right record sum. 15:0 left_sum left record sum table 181. record max registers bit field description 31:16 right_max right record max 15:0 left_max left record max a udio i nterface btv2300 register shadows btv2115 brook t ree 304 bt btv2300 register shadows the registers within the btv2300 are write-only and cannot be read directly by the btv2115. however, the btv2300 registers are ?hadowed?within the btv2115 so that software can read the last value written to the btv2300. this section de?es the shadowed registers. clock register name: aud_clk address: gbase | 005000c0h, read/write size: 16 bit function: the clock register is used by both the btv2115 and the btv2300 and controls the sample frequency and clock division for the aes encoder and decoder. two clocks are available: 16.9344 mhz (clk17) and 24.576 mhz (clk25), both speci?d to be +/- 0.01% in accuracy. the sel_clk17 ?ld selects which clock to use and is output to the audiostream interface via the audclk_out signal pin. clk_divisor is a 13-bit clock divider value used to load an up- counter (at the selected clock rate) to set the sample rate of audio, in- dependent of whether the data stream is mono or stereo. when a new clock divisor is written to this register, the clk_div_change bit is set. this bit is then reset after the new clock divisor is transmitted to the btv2300. refer to table 182 for bit content of the clock register. see table 183 for several representative examples. this register defaults to 00050200h (48khz, clk25). in some cas- es, this register performs like a shadow register. table 182. clock registers bits field description 15 reserved 14 clk_div_change 1= clock divisor changed (read only) 13 sel_clk17 1= use clk17 0 = use clk25 12:0 clk_divisor see table 183 a udio i nterface btv2300 register shadows btv2115 brook t ree 305 bt filter clock divisor register name: aud_fclk address: gbase | 005000c2h, read/write size: 8 bit function: this register contains the ?ter clock divisor, as shown in table 184. it is used to generate the clock within the btv2300 to drive an external switched-cap ?ter. either clk17 or clk25 (which ever is selected) is divided by two and then divided by this 6-bit divisor. the value of filter_divisor should be such that the ?ter clock is 50 (or 100) times the cut-off frequency, depending on the external ?ter in use. see the btv2300 audiostream interface speci?ation and associated appli- cation notes for more detailed information. codec mode register name: aud_cmode address: gbase | 005000c3h, read/write size: 8 bit function: this register contains the mode and con?uration information for the btv2300 audiostream interface. refer to table 185. table 183. sample rate examples sample frequency clock div,decimal div,hex 48,000 clk25 512 200 44,100 clk17 384 180 32,000 clk25 768 300 11,025 clk17 1536 600 8000 clk25 3072 c00 table 184. filter clock divisor bits field description 8:6 reserved 5:0 filter_divisor filter clock divisor (n-1) a udio i nterface btv2300 register shadows btv2115 brook t ree 306 bt application port direction register name: aud_appo address: gbase | 005000c4h, read/write size: 8 bit function: this register sets the bit-by-bit direction of the btv2300 application interface data register. 1= output, 0= input. application port write data register name: aud_appd address: gbase | 005000c5h, read/write size: 8 bit function: this register holds the data byte that will be or is being output on the btv2300 application interface data port. read data from the btv2300 applications port is available in aud_appr. table 185. codec mode register bits field description 7:6 io mode btv2300 io mode 00 = stereo out 01 = stereo in 10 = mono in, mono out 11 = reserved 5:4 adc_config btv2300 adc con?uration 00 = internal adc 01 = reserved 10 = reserved 11 = reserved 3:2 dac_config btv2300 dac con?uration 00 = internal dac 01 = reserved 10 = reserved 11 = reserved 1 tristate_btv2300_aes 1 = tristate btv2300 aes output 0= normal operation 0 select_aes_in 1 = route aes_in to serial audio out to btv2115. 0 = normal operation (adc to sa_out) a udio i nterface btv2300 register shadows btv2115 brook t ree 307 bt btv2300 mixer control register name: aud_mix address: gbase | 005000c6h, read/write size: 8 bit function: this register holds the shadow copy of the btv2300 mixer control reg- ister. refer to table 186 for bit content of this register. btv2300 mux selector register name: aud_mux address: gbase | 005000c7h, read/write size: 8 bit function: this register holds the shadow copy of the btv2300 mux selector reg- ister. refer to table 187 for bit content of this register. table 186. btv2300 mixer control register shadow bit field description 7:6 loop_test 00 = normal 01 = analog loopback, left 10 = analog loopback, right 11 = digital loopback 5 power_down 1 = powerdown 0 = normal 4:0 mixer_attenuation 00000 = mute 00001 = -51db 11111 = -6db table 187. btv2300 mux selector register shadow (1 of 2) bit field description 7 right_channel 1 = bits 5:0 update only right channel 0 = bits 5:0 update both left and right 6 recalibrate 1 =force a recalibrate operation in the btv2300 0 = normal operation a udio i nterface btv2300 register shadows btv2115 brook t ree 308 bt cd left attenuation register name: aud_cdl address: gbase | 005000c8h,read/write size: 8 bit function: this register shadows the btv2300 left cd attenuation register. refer to table 188 for bit content of this register. cd right attenuation register name: aud_cdr address: gbase | 005000c9h, read/write size: 8 bit function: this register shadows the btv2300 right cd attenuation register refer to table 189 for bit content of this register. 5 mic_mute 1 = pass the mic 0 = mute the mic 4 mux_gain 1 = +12db 0 = +6db 3 mix_gain 1 = +12db 0 = +6db 2:0 mixer_selector 000 = mute the mux 001 = cd analog 010 = line input 011 = fm synthesizer (opl3) 100 = mic 101 = mixer output 110 = dac output 111 = reserved table 188. cd left attenuation register bit field description 7:5 reserved 4:0 cd_left_atten 00000 = mute 00001 = -51db 11111 = -6db increment in steps of 1.5db per bit table 187. btv2300 mux selector register shadow (2 of 2) bit field description a udio i nterface btv2300 register shadows btv2115 brook t ree 309 bt line left attenuation register name: aud_ll address: gbase | 005000cah, read/write size: 8 bit function: this register shadows the btv2300 left line input attenuation register. refer to table 190 for bit content of this register. line right attenuation register name: aud_lr address: gbase | 005000cbh, read/write size: 8 bit function: this register shadows the btv2300 right line input attenuation register refer to table 191 for bit content of this register. table 189. cd right attenuation register bit field description 7:5 reserved 4:0 cd_right_atten 00000 = mute 00001 = -51db 11111 = -6db increment in steps of 1.5db per bit table 190. line input left attenuation register bit field description 7:5 reserved 4:0 line_left_atten 00000 = mute 00001 = -51db 11111 = -6db increment in steps of 1.5db per bit table 191. line input right attenuation bit field description 7:5 reserved 4:0 line_right_atten 00000 = mute 00001 = -51db 11111 = -6db increment in steps of 1.5db per bit a udio i nterface btv2300 register shadows btv2115 brook t ree 310 bt fm left attenuation register name: aud_fml address: gbase | 005000cch, read/write size: 8 bit function: this register shadows the btv2300 left fm synthesis input attenuation register. refer to table 192 for bit content of this register. fm right attenuation register name: aud_fmr address: gbase | 005000cdh, read/write size: 8 bit function: this register shadows the btv2300 right fm synthesis input attenua- tion register. refer to table 193 for bit content of this register. mic left gain register name: aud_micl address: gbase | 005000ceh, read/write size: 8 bit function: this register shadows the btv2300 left microphone input gain register. default value is 1fh (minimum gain). refer to table 194 for bit con- tent of this register. table 192. fm synthesis input left attenuation bit field description 7:5 reserved 4:0 fm_left_atten 00000 = mute 00001 = -51db 11111 = -6db increment in steps of 1.5db per bit table 193. fm synthesis input right attenuation bit field description 7:5 reserved 4:0 fm_right_atten 00000 = mute 00001 = -51db 11111 = -6db increment in steps of 1.5db per bit a udio i nterface btv2300 register shadows btv2115 brook t ree 311 bt mic right gain register name: aud_micr address: gbase | 005000cfh, read/write size: 8 bit function: this register shadows the btv2300 right microphone input gain regis- ter. a setting of zero implies in?ite gain, therefore is illegal. refer to table 195 for bit content of this register. dac left attenuation register name: aud_dacl address: gbase | 005000d0h, read/write size: 8 bit function: this register shadows the btv2300 left dac input attenuation register. refer to table 196 for bit content of this register. table 194. mic input left gain bit field description 7:5 reserved 4:0 mic_left_gain 00000 = illegal 00001 =+51db 11111 = +6db increment in steps of 1.5db per bit table 195. mic input right gain bit field description 7:5 reserved 4:0 mic_right_gain 00000 = illegal 00001 = +51db 11111 = +6db increment in steps of 1.5db per bit table 196. dac synthesis input left attenuation bit field description 7:5 reserved 4:0 dac_left_atten 00000= mute 00001 = -51db 11111 = -6db a udio i nterface btv2300 register shadows btv2115 brook t ree 312 bt dac right attenuation register name: aud_dacr address: gbase | 005000d1h, read/write size: 8 bit function: this register shadows the btv2300 right dac input attenuation regis- ter. refer to table 197 for bit content of this register. table 197. dac synthesis input right attenuation bit field description 7:5 reserved 4:0 dac_right _atten 00000 = mute 00001 = -51db 11111 = -6db a udio i nterface channel status btv2115 brook t ree 313 bt channel status the channel status ?ld for the audio output from btv2115 has two modes: either the values shown in table 198 or values from the playback channel status region of the frame buffer, depending on which mode is enabled. when not using channel status data from the frame buffer, the channel status block closely resembles the aes consumer format. table 198. channel status usage (1 of 3) byte professional (aes/ebu) consumer (s/pdif) 0 bits 7:6 = sample rate 00 = not indicated 01 = 44.1 khz 10 = 48 khz 11 = 32 khz bits 7:6 = mode 00 = mode 0 all others = reserved bit 5 = source locked 0 = sample rate locked 1 = sample rate unlocked bits 4:2 = emphasis 000 = not indicated 001 = no emphasis 011 = 50/15 m s 111 = ccitt j.17 all others = reserved bit 1 = mode 0 = digital audio 1 = digital data bits 5:3 = pre-emphasis (audio) 000 = none 001 = 50/15 m s - 2 channel 010 = reserved - 2 channel 011 = reserved - 2 channel 1xx = reserved - 4 channel - or - bits 5:3 = non-audio 000 = digital data all others = reserved bit 2 = copy protect 0 = copy inhibited/copyright asserted 1 = copy permitted/copyright not asserted bit 0 = channel format 0 = consumer 1= professional bit 1 = mode 0 = digital audio 1 = digital data bit 0 = channel format 0 = consumer 1 = professional a udio i nterface channel status btv2115 brook t ree 314 bt 1 bits 7:4 = user bits management 0000 = no user data indicated 1000 = 192 bit block 1100 = user de?ed operation all others = reserved (unde?ed) bits 3:0 = mode 0000 = not indicated 0010 = stereo 0100 = single channel (mono) 1000 = 2 channel 1100 = primary/secondary 1111 = vector to byte 3 all others = reserved bit 7 = mode 0 = consumer or professional 1 = program transfer mode if byte 0, bit 0 = 1 2 bits 7:6 = reserved (unde?ed) bits 5:3 = source word length a 000 = not indicated 001 = 20/16 bits 010 = 22/18 bits 100 = 23/19 bits 101 = 24/20 bits 110 = 21/17 bits all others = reserved bits 2:0 = auxiliary bits usage 000 = aux not de?ed (20-bit audio) 010 = single coordination signal (20- bit) 100 = used for sample data (24-bit) 110 = user de?ed operation all others = reserved 3 vector for multi-channel 8?0 (future) bits 7:6 = reserved bits 5:4 = clock accuracy 00 = level ii ( 1000 ppm) 01 = level i ( 50 ppm) 10 = level iii (variable) 11 = reserved bits 3:0 = sample frequency 0000 = 44.1 khz 0010 = 48 khz 0011 = 32 khz all others = reserved table 198. channel status usage (2 of 3) byte professional (aes/ebu) consumer (s/pdif) a udio i nterface channel status btv2115 brook t ree 315 bt 4 bits 7:2 = reserved bits 1:0 = reference signal c 00 = not reference signal 01 = grade 2 reference 10 = grade 1 reference 11 = reserved 5 reserved (8?0) 6:9 channel origin data d first character is byte 6 10:13 channel destination data d first character is byte 10 14:17 32-bit binary sample address code (incrementing every block). byte 14 is lsb 18:21 32-bit time-code. byte 18 is lsb e 22 validity bit 7 ?1 = bytes 18:21 are unreliable bit 6 ?1 = bytes 14:17 are unreliable bit 5 ?1 = bytes 6:13 are unreliable bit 4 ?1 = bytes 0:5 are unreliable bits 3:0 ?reserved (zeros) 23 crc f for bytes 0:22 a. notation is: number of bits for 24-bit max / number of bits for 20-bit max b. if the sample rate is exactly 48, 44.1, or 32 khz, that will be re?cted here; if some other sample rate is selected, ?ther?will be selected. in all cases, the sample rate information will be available via the user data block (though this is left up to software when using media buffer data for user data). c. digital audio reference signal per aes11-1990. d. 7-bit ascii data with odd parity bit. e. format is 00 hours, 00 minutes, 00 seconds, 00 frames, lsb ?st, where all zeros = midnight f. polynomial is g(x) = x p 8 + x p 4 + x p 3 + x p 2 + 1, with an initial state of all 1 s. table 198. channel status usage (3 of 3) byte professional (aes/ebu) consumer (s/pdif) brook t ree 317 bt o perating s pecifications vram timing parameters memory interface operation of btv2115 is controlled by the bit value contained in grp_cfg0[6:5]. this determines the ram timing characteristics of the memory interface. the columns in table 199 below indicate the characteristics of the memory interface relative to the settings of grp_cfg0[6:5]. the timing of bios cycles is determined by the bit value contained in grp_cfg1[5]. bios cycles, opl cycles, and the timing of the pacdac interface are inde- pendent of the grp_cfg0[6:5] value. the timings for bios, opl, and pacdac are replicated across the grp_cfg0[6:5] columns solely for clarity. table 199. btv2115 output speci?ations for dram signals (1 of 6) parameter description symbol 11 10 01 00 notes min max min max min max min max ns ns ns ns cycle time, cas-before-ras refresh cbrc 170 176 170 176 170 176 170 176 1 cycle time, read rc 120 124 120 124 139 145 160 166 cycle time, write wc 119 125 119 125 139 145 160 166 cycle time, load color register lcrc 170 176 170 176 170 176 170 176 1 cycle time, block write bwc 119 125 119 125 139 145 160 166 cycle time, memory to register transfer rtc 119 125 119 125 139 145 160 166 cycle time, page mode write pmwc 37 43 37 43 58 64 58 64 cycle time, page mode read pmrc 37 43 58 64 58 64 58 64 cycle time, rom read romrc 241 247 241 247 241 247 241 247 1,6 cycle time, flash rom write romwc 241 247 241 247 241 247 241 247 1,6 cycle time, rom read romrc 78 84 78 84 78 84 78 84 1,7 o perating s pecifications vram timing parameters btv2115 brook t ree 318 bt cycle time, flash rom write romwc 68 74 68 74 68 74 68 74 1,7 cycle time, opl read oplrc 220 226 220 226 220 226 220 226 1 cycle time, opl write oplwc 200 206 200 206 200 206 200 206 1 ras precharge rpcbr 88 94 88 94 88 94 88 94 1 ras pulse width rascbr 88 94 88 94 88 94 88 94 1 cas precharge cpcbr 68 74 68 74 68 74 68 74 1 cas setup to ras csr 17 23 17 23 17 23 17 23 1 dsf setup to ras fsrcbr 17 23 17 23 17 23 17 23 1,2 dsf hold from ras low rfhcbr 17 23 17 23 17 23 17 23 1,2 cas hold from ras low chr 88 94 88 94 88 94 88 94 1 ras precharge rp 48 52 48 52 58 62 68 72 ras pulse width ras 70 74 70 74 80 84 90 94 cas precharge cp 18 22 18 22 28 32 28 32 cas pulse width cas 39 43 39 43 49 53 59 63 ras low to cas low delay rcd 27 33 27 33 27 33 27 33 1 address setup to ras asr 8 12 8 12 8 12 8 12 1 row address hold rah 18 22 18 22 18 22 18 22 1 address setup to cas asc 8 12 8 12 8 12 8 12 1 column address hold cah 28 32 28 32 38 42 48 52 trg high setup to ras tsr 48 54 48 54 58 64 68 74 trg high hold from ras low rth 28 34 28 34 28 34 28 34 1 trg pulse width trg 38 44 38 44 48 54 58 64 read data setup to end of cycle rds 3- 3- 5- 7- 3 read data hold from end of cycle rdh 0- 0- 0- 0- 3 we high (read) hold from cas rch 38 44 38 44 38 44 38 44 1 dsf setup to ras fsr 48 54 48 54 58 64 68 74 dsf hold from cas low cfh 38 44 38 44 48 54 58 64 mask setup to ras ms 8 12 8 12 8 12 8 12 1 table 199. btv2115 output speci?ations for dram signals (2 of 6) parameter description symbol 11 10 01 00 notes min max min max min max min max ns ns ns ns o perating s pecifications vram timing parameters btv2115 brook t ree 319 bt mask hold from ras low mh 18 22 18 22 18 22 18 22 1 data setup to cas ds 9 13 9 13 9 13 9 13 1 data hold from cas low dh 38 42 38 42 48 52 58 62 we low (write) setup to ras wsr 17 23 17 23 17 23 17 23 1 we low (write) hold from cas wch 38 44 38 44 48 54 58 64 trg high (write) setup to ras ys 48 54 48 54 58 64 68 74 trg high (write) hold from ras low yh 68 74 68 74 78 84 88 94 we high hold from ras low rwhlcr 18 22 18 22 18 22 18 22 1,4 we low setup to cas wsclcr 8 12 8 12 8 12 8 12 1 dsf hold from ras low fhr 48 54 48 54 58 64 68 74 1 we hold from ras low rwh 18 22 18 22 18 22 18 22 1 we low setup to cas wsc 8 12 8 12 8 12 8 12 1 dsf hold from ras low rfh 17 23 17 23 17 23 17 23 1 dsf setup to cas fsc 8 12 8 12 8 12 8 12 1 cas precharge, page mode cppm 18 22 18 22 28 32 28 32 cas pulse width, page mode read casrpm 19 23 29 33 29 33 29 33 cas pulse width, page mode write caswpm 19 23 19 23 29 33 29 33 address setup to cas, page mode ascpm 8 12 8 12 8 12 8 12 1 address hold from cas low, page mode cahpm 18 22 18 22 18 22 18 22 1 we setup to cas, page mode wscpm 8 12 8 12 8 12 8 12 1 we hold from cas low, page mode wchpm 8 12 8 12 8 12 8 12 1 trg setup to cas, page mode tscpm 8 12 8 12 8 12 8 12 1 trg hold from cas low, page mode tchpm 17 23 17 23 17 23 17 23 1 data setup to cas, page mode dspm 9 13 9 13 9 13 9 13 1 table 199. btv2115 output speci?ations for dram signals (3 of 6) parameter description symbol 11 10 01 00 notes min max min max min max min max ns ns ns ns o perating s pecifications vram timing parameters btv2115 brook t ree 320 bt date hold from cas low, page mode dhpm 18 22 18 22 18 22 18 22 1 dsf setup to cas, page mode fscpm 8 12 8 12 8 12 8 12 1 dsf hold from cas low, page mode cfhpm 17 23 17 23 17 23 17 23 1 refresh cycle ref --------1,5 mdata setup to bios_cs mscrom 38 44 38 44 38 44 38 44 1,6 bios_cs setup to we cswrom 17 23 17 23 17 23 17 23 1,6 bios_cs hold from we chwrom 17 23 17 23 17 23 17 23 1,6 mdata hold from bios_cs mhcrom 28 34 28 34 28 34 28 34 1,6 bios_cs pulse width csrom 180 186 180 186 180 186 180 186 1,6 we pulse width werom 139 145 139 145 139 145 139 145 1,6 bios_cs setup to trg cstrom 18 22 18 22 18 22 18 22 1,6 bios_cs hold from trg chtrom 18 22 18 22 18 22 18 22 1,6 trg pulse width trgrom 139 145 139 145 139 145 139 145 1,6 bios_cs precharge csprom 109 115 109 115 109 115 109 115 1,6 bios_cs setup to we cswrom 7 13 7 13 7 13 7 13 1,7 bios_cs hold from we chwrom 17 23 17 23 17 23 17 23 1,7 bios_cs pulse width csrom 68 74 68 74 68 74 68 74 1,7 we pulse width werom 38 44 38 44 38 44 38 44 1,7 bios_cs setup to trg cstrom 7 13 7 13 7 13 7 13 1,7 bios_cs hold from trg chtrom 17 23 17 23 17 23 17 23 1,7 mdata setup to trg dsrom 20 - 20 - 20 - 20 - 1,7 mdata hold from trg dhrom 0 - 0 - 0 - 0 - 1,7 trg pulse width trgrom 68 74 68 74 68 74 68 74 1,7 bios_cs precharge csprom 58 64 58 64 58 64 58 64 1,7 mdata setup to trg mstopl 7 13 7 13 7 13 7 13 1 table 199. btv2115 output speci?ations for dram signals (4 of 6) parameter description symbol 11 10 01 00 notes min max min max min max min max ns ns ns ns o perating s pecifications vram timing parameters btv2115 brook t ree 321 bt trg low setup to opl_cs tscopl -3 3 -3 3 -3 3 -3 3 1 trg hold from opl_cs thcopl -3 3 -3 3 -3 3 -3 3 1 mdata hold from trg mhtopl 17 23 17 23 17 23 17 23 1 opl_cs pulse width csopl 160 166 160 166 160 166 160 166 1 trg pulse width trgopl 160 166 160 166 160 166 160 166 1 data setup to opl_cs dsopl 10 - 10 - 10 - 10 - data hold from opl_cs dhopl 2 - 2 - 2 - 2 - opl_cs precharge cspopl 282 288 282 288 282 288 282 288 1 mdata setup to we mswopl 7 13 7 13 7 13 7 13 1 we low setup to opl_cs wscopl 7 13 7 13 7 13 7 13 1 we hold from opl_cs whcopl -3 3 -3 3 -3 3 -3 3 1 mdata hold from we mhwopl 7 13 7 13 7 13 7 13 1 we pulse width weopl 170 176 170 176 170 176 170 176 1 sclk cycle time sc 13.3 - 13.3 - 13.3 - 13.3 - 1 sclk precharge sch 6 - 6 - 6 - 6 - 1 sclk pulse width scl 6 - 6 - 6 - 6 - 1 lclk cycle time lc 13.3 - 13.3 - 13.3 - 13.3 - 1 lclk precharge lch 6 - 6 - 6 - 6 - 1 lclk pulse width lcl 6 - 6 - 6 - 6 - 1 table 199. btv2115 output speci?ations for dram signals (5 of 6) parameter description symbol 11 10 01 00 notes min max min max min max min max ns ns ns ns o perating s pecifications vram timing parameters btv2115 brook t ree 322 bt lclk0 to lclk1 skew llsk 181818181 pt setup to lclk0 psl 1 - 1 - 1 - 1 - 1 pt hold from lclk0 high plh 3 - 3 - 3 - 3 - 1 soe setup to ?st lclk0 ris- ing edge sosl 40 - 40 - 40 - 40 - 1,8 soe hold from last lclk0 ris- ing edge solh 40 - 40 - 40 - 40 - 1,8 notes: 1. values are independent of grp_cfg0[6:5] setting. 2. the state of dsf during cas-before-ras cycles is programmable via grp_cfg0[0], see table 26 on page 54 3. end of cycle is determined by the rising edge of either cas or ras, which ever occurs ?st. 4. applies only to lcr (load color register) cycles. 5. the refresh rate is programmable by writing grp_cfg2 (con?uration register 2, refresh rate counter), see table 24 on page 53. 6. these timing are valid for grp_cfg1[5] = 0, 120 nsec rom cycles. 7. these timing are valid for grp_cfg1[5] = 1, 70nsec rom cycles. 8. soe always switches before the 1st dword of the next packet group is sent. ?irst lclkx rising edge?refers to this 1st dword. ?ast lclkx rising edge?refers to the last packet sent prior to subsequent soe change for the next packet group. table 199. btv2115 output speci?ations for dram signals (6 of 6) parameter description symbol 11 10 01 00 notes min max min max min max min max ns ns ns ns o perating s pecifications vram timing parameters btv2115 brook t ree 323 bt btv2115 subsystem vram load limits btv2115 is designed to drive up to 8 vram modules, with considerations for ad- ditional rom and a yamaha fm synthesizer. table 200 shows the load limits for the modules. table 200. btv2115 load limits signal capacitive, pf min max mdata[7:0] 85 mdata[10:8] 85 mdata[27:11] 85 mdata[31:28] 85 maddr[9:0] 60 ras [3:0] 40 cas [3:0] 40 we 050 we 150 trg 85 dsf 70 soe [3:0] 40 ldclk0 50 ldclk1 50 pt[3:0] 25 o perating s pecifications absolute maximum ratings btv2115 brook t ree 324 bt absolute maximum ratings table 201. absolute maximum ratings parameter symbol min typ max units vaa, vdd (measured to gnd) 7.0 v voltage on any signal pin gnd ?0.5 vdd + 0.5 v ambient operating temperature t a ?5 +125 ?c storage temperature t s ?5 +150 ?c junction temperature t j +150 ?c vapor phase soldering (1 minute) t vsol 220 ?c stresses above those listed in this table may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?ation are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device employs high-impedance cmos devices on all signal pins. it should be handled as an esd-sensi- tive device. voltage values on any signal pin that extend beyond the power supply rails by more than the amount(s) speci?d above can cause destructive latchup. o perating s pecifications recommended operating conditions btv2115 brook t ree 325 bt recommended operating conditions table 202. recommended operating conditions parameter min typ max units load capacitance on digital outputs: pf trg 80 85 pf dsf 60 70 pf maddr 45 60 pf mdata 40 85 pf cas [3:0] 35 40 pf we [1:0] 35 50 pf ras [3:0] 35 40 pf soe [3:0] 35 40 pf bios_cs 20 pf opl_cs 20 pf pt[3:0] 20 25 pf reset_out 80 pf load capacitance on io pins vl_data[31:0], list of io pins tbd pf load capacitance on clock outputs : lckl[1:0], audclk_out 60 tbd pf supply voltage 4.75 5.00 5.25 v junction temperature t j 0 125 ?c o perating s pecifications target dc characteristics btv2115 brook t ree 326 bt target dc characteristics target dc characteristics are shown in table 203, ii2 characteristics in table 204, and ddc characteristics in table 205. power dissipation ?ures are shown in figure 59 and figure 60. table 203. target dc characteristics parameter symbol min typ max units digital inputs input high voltage input low voltage v ih v il 2.0 gnd?.5 v dd + 0.5 0.8 v v input high current (v in = 2.4 v) input low current (v in = 0.4 v) i ih i il ?0 10 m a m a input capacitance (v = 1 mhz, vin = 2.4 v) c in 7pf hysteresis if applicable 0.3 v digital outputs output high voltage (i oh = ?00 m a) v oh 2.4 v output low voltage (i ol = 3.2 ma) v ol 0.4 v three-state current (0?.4v) i oz 50 m a o perating s pecifications target dc characteristics btv2115 brook t ree 327 bt table 204. dc characteristics for iic_sda and iic_scl i/o (fast mode) parameter symbol min. max. units low level input voltage v il ?.5 1.5 v high level input voltage v ih 3.0 v dd + 0.5 v hysteresis v hys 0.2 v spike suppression t sp 050ns low level output voltage (open drain) at 3 ma sink current at 6 ma sink current v ol1 v ol2 0.4 0.6 v v output fall time (10?00pf bus capacitance) t of 20 + 0.1c b 1 250 2 ns input current (vi = 0.4?.9v dd max. )i i ?0 10 m a capacitance c i 10 pf 1. c b = capacitance of one bus line in pf. 2. sda and scl lines will not be obstructed if v dd is switched off. table 205. dc characteristics for ddc_sda and ddc_scl i/o (standard mode) parameter symbol min. max. units low level input voltage v il ?.5 1.5 v high level input voltage v ih 3.0 v dd + 0.5 v hysteresis v hys 0.2 v spike suppression t sp 050ns low level output voltage (open drain) at 3 ma sink current at 6 ma sink current v ol1 v ol2 0.4 0.6 v v output fall time (10?00pf bus capacitance) t of 20 + 0.1c b 1 250 2 ns input current (vi = 0.4?.9v dd max . )i i ?0 10 m a capacitance c i 10 pf 1. c b = capacitance of one bus line in pf. 2. sda and scl lines will not be obstructed if v dd is switched off. o perating s pecifications target ac characteristics btv2115 brook t ree 328 bt target ac characteristics table 206 and table 207 provide the target ac characteristics for the i2c bus. table 206. ac characteristics for iic_sda and iic_scl bus lines (fast mode) parameter symbol min. max units scl clock frequency 0 400 khz bus free time between a stop and start condition 1.3 m s hold time (repeated) start condition. after this period, the ?st clock pulse is generated 0.6 m s low period of the scl clock 1.3 m s high period of the scl clock 0.6 m s set-up time for a repeated start condition 0.6 m s data hold time 0 0.9 m s data set-up time 100 m s rise time of both sda and scl signals 20 + 0.1c b 1 300 ns fall time of both sda and scl signals 20 + 0.1c b 1 300 ns set-up time for stop condition 0.6 m s capacitive load for each bus line 400 pf 1. sda and scl lines will not be obstructed if v dd is switched off. table 207. ac characteristics for ddc_sda and ddc_scl bus lines (standard mode) (1 of 2) parameter symbol min. max units scl clock frequency 0 400 khz bus free time between a stop and start condition 1.3 m s hold time (repeated) start condition. after this period, the ?st clock pulse is generated 0.6 m s low period of the scl clock 1.3 m s high period of the scl clock 0.6 m s set-up time for a repeated start condition 0.6 m s data hold time 0 0.9 m s o perating s pecifications target ac characteristics btv2115 brook t ree 329 bt data set-up time 100 m s rise time of both sda and scl signals 20 + 0.1c b 1 300 ns fall time of both sda and scl signals 20 + 0.1c b 1 300 ns set-up time for stop condition 0.6 m s capacitive load for each bus line 400 pf 1. sda and scl lines will not be obstructed if v dd is switched off. table 207. ac characteristics for ddc_sda and ddc_scl bus lines (standard mode) (2 of 2) parameter symbol min. max units o perating s pecifications power dissipation btv2115 brook t ree 330 bt power dissipation introduction a system designer should consider the cost/reliability trade-offs when determining package selection and cooling requirements. as a rule, the device junction temper- ature should not exceed 125 ? c to prevent compromising device reliability. the in- formation in this section provides the data needed to determine the best trade-offs. power dissipation the following factors affect device thermal performance: air ?w, ambient tem- perature, board thermal characteristics (including copper area and thickness), package thermal characteristics, device power dissipation, power dissipation of surrounding devices, and board power dissipation. these trade-off considerations assume that the surrounding devices do not contribute nor block heat dissipation and do not block air?w. it is also assumed that the circuit board contains a set amount of copper (combined weight, all layers). thermal resistance the ability of a package to dissipate power is characterized by the overall thermal resistance of the package. the thermal resistance of the available packages is de- termined based on experimental data. device junction to ambient thermal resis- tance is commonly denoted by the symbol q ja . packages having decreased thermal resistance are generally more expensive due to the inclusion of heat slugs, heat spreaders, more expensive lead frames, etc. the thermal resistance of a given package can also be reduced by providing air?w over the package. table 208 shows the thermal resistance for the die junction packages shown in figure 59 and figure 60. package power dissipation the thermal resistance of a package as a function of power dissipation and junction and ambient temperatures is computed using the following expression: table 208. package thermal resistance package air?w (linear feet per minute) units 0 50 100 200 400 208-pin power quad 17 15 13 12 10 ?c/w 208-pin mqfp 21 19 17 16 14 ?c/w q ja t j t a p ----------------- = o perating s pecifications power dissipation btv2115 brook t ree 331 bt the btv2115 s worst case power dissipation (icc, max, @ vcc, max) is 3.3 w. figure 59 charts the worst case die junction temperature versus air ?w for the power quad. figure 60 charts the worst case die junction temperature versus air ?w for the heat spreader 208mqfp. where: t j = junction temperature t a = ambient temperature q ja = package thermal resistance p = resulting package power dissipation figure 59. worst case power dissipation for power quad air flow (lfpm) die junction temp (deg c) 50 75 100 125 150 0 50 100 150 200 250 300 350 400 30 c ambient 40 c ambient 50 c ambient 60 c ambient 70 c ambient 125 c max junction o perating s pecifications power dissipation btv2115 brook t ree 332 bt recommendations by using the worst case power dissipation ?ures for a desired mode of operation and environment, one can deduce the required package thermal resistance. the system designer may then choose the appropriate package. suppose that the system designer wants to use the heat spreader package in an environment where no air ?w can be guaranteed. with a power dissipation of 3.3 w and a maximum recommended operating junction temperature of 125 o c, a maximum ambient temperature can be calculated. rearranging the thermal resis- tance equation yields: t a = t j - q ja p so: t a = 125 - 21(3.3) or 55.7 o c figure 60. worst case power dissipation for heat spreader mqfp air flow (lfpm) die junction temp (deg c) 50 75 100 125 150 0 50 100 150 200 250 300 350 400 30 c ambient 40 c ambient 50 c ambient 60 c ambient 70 c ambient 125 c max junction o perating s pecifications timing diagrams btv2115 brook t ree 333 bt timing diagrams this section contains vram timing diagrams. for related timing information, refer to ?l bus timing?on page 213. figure 61. vram read cycle maddr rasx casx trg mdata wex dsf row column valid rp ras cp rcd cas asr rah asc cah tsr rth trg rds rdh fsr cfh rch rc o perating s pecifications timing diagrams btv2115 brook t ree 334 bt figure 62. vram masked write cycle maddr rasx casx mdata wex dsf column row valid mask rp ras cp rcd cas asr rah asc cah ms mh ds dh wsr wch fsr cfh trg tsr yh wc o perating s pecifications timing diagrams btv2115 brook t ree 335 bt figure 63. load color register cycle figure 64. cas-before-ras refresh cycles maddr rasx casx mdata wex dsf column row valid rp ras cp rcd cas asr rah asc cah ds dh wsr rwhlcr wcslcr wch fsr fhr lcrc rascbr ras x we x dsf trg casx fsrcbr rfhcbr cascbr rpcbr cbrc cpcbr chr csr o perating s pecifications timing diagrams btv2115 brook t ree 336 bt figure 65. vram non-masked block write cycle figure 66. vram memory-to-shift register transfer cycle maddr rasx casx mdata wex dsf column row valid rp ras cp rcd cas asr rah asc cah ds dh wsr rwh wsc wch fsr rfh fsc cfh fhr bwc maddr rasx casx trg mdata wex dsf column row rp ras cp rcd cas asr rah asc cah ys yh wsr wch fsr cfh rtc o perating s pecifications timing diagrams btv2115 brook t ree 337 bt figure 67. page mode cycles maddr rasx casx trg mdata wex dsf { { { write read block write caspm cppm caspm cppm caspm cppm ascpm cahpm ascpm cahpm ascpm cahpm wscpm wchpm tscpm tchpm rds rdh dspm dhpm wscpm wchpm dhpm dspm fscpm cfhpm pmwc pmrc pmwc o perating s pecifications timing diagrams btv2115 brook t ree 338 bt figure 68. rom read cycle figure 69. rom write cycle, flash rom bios_cs trg rom address mdata[27:8] valid mdata[7:0] cstrom mscrom mhcrom csrom dhrom dsrom csprom chtrom trgrom romrc bios_cs we write data mdata[7:0] mdata[27:8] mscrom cswrom csrom werom csprom mhcrom chwrom address romwc o perating s pecifications timing diagrams btv2115 brook t ree 339 bt figure 70. opl read cycle figure 71. opl write cycle opl_cs trg opl address mdata[27:8] valid mdata[7:0] tscopl mstopl mhtopl csopl dhopl dsopl cspopl thcopl trgopl oplrc opl_cs we opl address mdata[27:8] wscopl mswopl mhwopl csopl cspopl whcopl weopl mdata[7:0] write data oplwc o perating s pecifications timing diagrams btv2115 brook t ree 340 bt figure 72. pacdac controller interface lsync scl sch ldclk1 ldclk0 sclk sc lch lch llsk lc lssc lsch soe [3:0] plh psl pt[3:0] solh sosl lc lcl lcl o perating s pecifications packaging speci?ations btv2115 brook t ree 341 bt packaging speci?ations figure 73 shows model btv2115ksf: power quad package with exposed heat slug. figure 74 shows model BTV2115AHF: plastic qfp with an internal heat spreader. figure 73. btv2115ksf packaging diagram o perating s pecifications packaging speci?ations btv2115 brook t ree 342 bt figure 74. BTV2115AHF packaging diagram o perating s pecifications btv2115 vl-bus pin layout btv2115 brook t ree 343 bt btv2115 vl-bus pin layout figure 75 shows the pin assignments for vl-bus interface to the btv2115. refer to table 1 on page 11 for a descrip- tive summary of each pin. figure 75. vl-bus pin layout vdd mm_clk mm_data7 mm_data6 mm_data5 mm_data4 mm_data3 mm_data2 mm_data1 mm_data0 v_pll g_pll sa_in opl_irq tm2 n_c audclk_out sa_out reset_out aes_out bios_cs opl_cs irq9 vl_ldev vl_lrdy vdd gnd tm1 tm0 vl_id2 vl_rdyrtn vl_w_r vl_ads vl_m_io vl_be3 vl_d_c vl_be2 vl_reset vl_be1 vl_addr2 vl_be0 vdd vl_clock gnd vl_addr3 vl_addr4 vl_addr5 vl_addr6 vl_addr7 vl_addr9 vl_addr8 vl_addr11 vdd maddr3 maddr2 cas2 cas3 maddr1 maddr0 dsf vdd gnd ras0 soe0 ras1 soe1 ras2 soe2 ras3 soe3 vdd lclk1 gnd pt0 pt1 pt2 pt3 gnd lclk0 vdd sclk gnd clk17 gnd clk25 vrdy lsync gnd vdd vl_data0 vl_data1 vl_data2 vl_data3 ddc_scl ddc_sda vl_data4 vl_data5 vl_data6 vl_data7 vl_data8 vl_data9 vl_data10 vl_data11 vdd btv2115 gnd mdata31 mdata30 mdata29 mdata28 mdata27 mdata26 mdata25 mdata24 mdata23 mdata22 mdata21 mdata20 gnd vdd mdata19 mdata18 mdata17 mdata16 mdata15 mdata14 mdata13 mdata12 mdata11 mdata10 gnd vdd mdata9 mdata8 mdata7 mdata6 mdata5 mdata4 mdata3 gnd vdd mdata2 mdata1 mdata0 we1 we0 trg maddr8 gnd vdd maddr7 maddr6 cas0 cas1 maddr5 maddr4 gnd vl_addr10 vl_addr13 vl_addr12 vl_addr14 vl_addr15 vl_addr16 vl_addr17 vl_addr18 gnd vdd iic_scl iic_sda vl_addr19 vl_addr20 vl_addr21 vl_addr22 vl_addr23 vl_addr24 vl_addr25 vl_addr27 vl_addr26 vl_addr29 vl_addr28 vl_addr30 vl_addr31 gnd vdd vl_data31 vl_data30 vl_data29 vl_data28 vl_data27 vl_data26 vl_data25 vl_data24 gnd vdd vl_data23 vl_data22 vl_data21 vl_data20 vl_data19 vl_data18 vl_data17 gnd vdd vl_data16 vl_data14 vl_data15 vl_data13 vl_data12 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 vl-b us o perating s pecifications btv2115 pci-bus pin layout btv2115 brook t ree 344 bt btv2115 pci-bus pin layout figure 76 shows the pin assignments for the pci bus interface to the btv2115. refer to table 2 on page 15 for a de- scriptive summary of each pin. figure 76. pci-bus pin layout vdd mm_clk mm_data7 mm_data6 mm_data5 mm_data4 mm_data3 mm_data2 mm_data1 mm_data0 v_pll g_pll sa_in opl_irq tm2 pci_inta audclk_out sa_out reset_out aes_out bios_cs opl_cs pci_nc0 pci_nc1 pci_nc2 vdd gnd tm1 tm0 hsread pci_pdn0 pci_pdn1 pci_pdn2 pci_pdn3 pci_pdn4 pci_pdn5 pci_pdn6 pci_rst pci_pdn7 mm_data16 pci_pdn8 vdd pci_clk gnd mm_data17 mm_data18 mm_data19 mm_data20 mm_data21 mm_data23 mm_data22 mm_data9 vdd maddr3 maddr2 cas2 cas3 maddr1 maddr0 dsf vdd gnd ras0 soe0 ras1 soe1 ras2 soe2 ras3 soe3 vdd lclk1 gnd pt0 pt1 pt2 pt3 gnd lclk0 vdd sclk gnd clk17 gnd clk25 vrdy lsync gnd vdd pci_ad0 pci_ad1 pci_ad2 pci_ad3 ddc_scl ddc_sda pci_ad4 pci_ad5 pci_ad6 pci_ad7 pci_ad8 pci_ad9 pci_ad10 pci_ad11 vdd btv2115 gnd mdata31 mdata30 mdata29 mdata28 mdata27 mdata26 mdata25 mdata24 mdata23 mdata22 mdata21 mdata20 gnd vdd mdata19 mdata18 mdata17 mdata16 mdata15 mdata14 mdata13 mdata12 mdata11 mdata10 gnd vdd mdata9 mdata8 mdata7 mdata6 mdata5 mdata4 mdata3 gnd vdd mdata2 mdata1 mdata0 we1 we0 trg maddr8 gnd vdd maddr7 maddr6 cas0 cas1 maddr5 maddr4 gnd mm_data8 mm_data11 mm_data10 mm_data12 mm_data13 mm_data14 mm_data15 pci_pdn9 gnd vdd iic_scl iic_sda pci_pdn10 pci_pdn11 pci_id sel c_be3 c_be2 pci_frame pci_irdy pci_trdy pci_devsel pci_stop pci_par c_be1 c_be0 gnd vdd pci_ad31 pci_ad30 pci_ad29 pci_ad28 pci_ad27 pci_ad26 pci_ad25 pci_ad24 gnd vdd pci_ad23 pci_ad22 pci_ad21 pci_ad20 pci_ad19 pci_ad18 pci_ad17 gnd vdd pci_ad16 pci_ad14 pci_ad15 pci_ad13 pci_ad12 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 pci b us o perating s pecifications revision history btv2115 brook t ree 345 bt revision history table 209. btv2115 datasheet revision history revision date change description a 9/20/94 initial release b 12/16/94 c 2/3/95 initial release c 8/30/95 update |
Price & Availability of BTV2115AHF
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |